SU860053A1 - Bcd-to-binary fraction converter - Google Patents

Description

The invention relates to automation and computing and can be used in the construction of binary-decimal converters. A known binary fraction converter is a binary fraction containing a tetrade register, a high-order register, a decoder, a group of elements And, an adder, a generator, a driver, an overhead information register, an address counter, a binary order register, a memory block. The conversion in this device is based on summing up the binary coefficients of the tetrads followed by y; multiplying by the binary coefficient, which is one-to-one in decimal order 1. The disadvantage of this converter is relatively slow performance. The binary is the closest to the one proposed by the technical nature. - a fractional binary fraction containing a tetrad register, whose input is the information input of the converter, the first decoder, the group of elements AND, the sum torus, pulse generator, the input of which is the start input of the converter, pulse distributor, service information register, address counter, binary order register, first memory block whose input is connected to the output of the address counter, the output of the tetrad register is connected to the information input of the first the decoder, the output of which is connected to the first inputs of the elements AND groups, the outputs of which are connected to the input of the adder, the outputs of the adder are the outputs of the mantissa of the converter, the output of the pulse generator is connected to that The first input of the pulse distributor, the control input of which is the control input of the converter, the first information input of the pulse distributor is connected to the first output of the service information register, the first, second and third inputs of which are respectively the input of the decimal order of the converter, the sign input of the order the converter and the input of the attribute of the decimal mantissa of the converter, the second output of the service information register is connected to the second information input of the pulse distributor and The first input of the address counter, the second input of which is connected to the third output of the service information register and the third information input of the pulse distributor, the first, second, third and fourth outputs of which are connected respectively to the clock inputs of the register of the interceptor, the first decoder, cviviMaTopa and the address counter, the first the output of the binary order register is the output of the order of converter 2; the disadvantage of the known converter is also a relatively low speed associated with the need to multiply nor polnorazr d numbers. The purpose of the invention is to increase speed. The goal is achieved by the fact that the 3rd converter of the binary-decimal fraction in binary fraction is additionally introduced a shifter, a second decoder, a second memory block, the input of which is connected to the output of the second decoder, and the output is connected to the input of the binary order register, the second output of which is connected with the control inputs of the shifter, the information input of which is connected to the output of the first memory block, the output of the shifter is connected to the second inputs of the elements of the group, and the first, second and third inputs of the second decoder co dineny respectively to the fifth output pulse distributor second and third outputs of the register service information. In addition, in the converter, the address counter is reversible. The drawing shows the block diagram of the proposed Converter. The circuit includes information input 1, register 2 tetrads, first decoder 3, group of elements 4, sumator 5, outputs 6 of the mantissa of the converter, input 7 start of the converter, 8 pulse generator, distributor 9 pulses, control input 10 of the converter, input 11 decimal order of converter, input 12 characters of order of converter, input 13 of sign of decimal mantissa of converter, register of service information 14, reversible counter 15 of the clock, register of 16 binary order, output of 17 as a converter, first memory block 18, sd The driver 19, the second decoder 20, the second memory block 21. Control input 10 serves to supply a control signal from an input device (not shown). The first output of the distributor 9 pulses is connected to the output of the register of 2 tetrads to shift its contents by two positions in the direction of the lower bits. The second and third outputs of the distributor 9 pulses, respectively, are connected to the second input of the first decoder and the input of the adder 5 to signal the analysis and shift the contents of the adder 5 by two positions in the direction of the lower bits. The output of the first memory block 18 is connected to the first input of the shifter 19 for supplying the binary equivalent of type 10. The output of the second decoder 20 is connected to the input of the second memory unit 21 storing binary orders. The output of the shifter | 19 is connected to the second input of the elements AND 4 groups for the transfer of the set-up binary equivalent of the type 2 The transformation is carried out in accordance with the following relation A - ST,), C) i - i where A is the binary mantissa ; m is a binary order; i is the number of the decimal digit; T is the tetrad of the decimal number; P - decimal order, (0) 2 reduced binary equivalent. The conversion of the binary-decimal number is based on the summation of the products of the decimal tetrads by the given binary equivalent and the assignment of the required binary order to the result. Moreover, the reduced binary equivalent (10-1, -2 is obtained from the binary equivalent stored in the first memory block 18 by shifting by 2. The relationship (1) is implemented in the following sequence. Input 7 receives the Start signal to the pulse generator B, which produces a series of pulses. This series arrives at the pulse distributor 9. Then, the decimal order and decimal order and the sign of the decimal mantissa are input alternately at inputs 11 to 13. The input 1 at register 2 tetrads alternately. fasting The highest tetrad of the converted binary-decimal number is fed in. Simultaneously, a control signal arrives at input 10. The distributor 9 starts up, ensuring the normal operation of the entire converter. In the first cycle, the counter 15 sets some address, which is determined by the magnitude and sign of the decimal In the second cycle, it changes its state by one (negative for, positive for), thereby setting the true address of the access to memory block 18. The counter 15 GW is made reversible, i.e. It works in two modes: the mode of subtraction and summation of pulses. In this case, in the second cycle of the first cycle, it operates in the pulse subtraction mode, in all subsequent cycles in the pulse summing mode. At the same time, in the second clock, the decryphrato 20 sets the address of access by the second memory block 21. In the third cycle, the first and second blocks 18 and 21 of memory are read. In this case, from the first memory block 18, reads the binary equivalent of the form corresponding to the highest tetrad stored on the register 2 tetrads. The first memory block 18 stores binary equivalents. If there were no shifter 19, then it would be necessary to store arrays of 1 binary equivalents each. The shifter 19 together with the binary order register 16 allows to obtain the necessary reduced binary equivalents. In the fourth cycle, a reduced binary equivalent of 10 2 is produced by shifting the binary equivalent received at the input of the shifter 19 by the amount stored in the binary order register 16. The direction of the shift is determined by the sign bit after it. The shifter 19 is structurally designed in the form of several stages, each of which transmits information either with a shift or without shifting depending on whether a zero or one has a corresponding register bit 16. In the first time, the first descriptor 3 analyzes the state of the next pair of bits The register of 2 tetrads is transmitted and the given binary equivalence is transmitted through the group of elements 5V and 4 to the adder 5. In this case, the decoder 3 produces three types of transmissions: a memory with a code, a direct code with a shift by one position towards the older ones bits, additional code. In the mecTQM cycle, the transmitted information is summed with the contents of adder 5. In the seventh cycle, the lower bits are shifted by two positions of the contents of the register 2 tetrads and the adder 5. On the eighth cycle, the first decoder 3 analyzes the state of the lower pair of bits of register 2 and transfers the binary equivalent from the shifter 19 to the adder 5 or forward code, or a direct code with a shift of one position in the direction of higher bits, or an additional code. The ninth cycle is the summation of the contents of the adder 5 with the first partial product. This completes the conversion cycle of the highest tetrad.

With the arrival of subsequent tetrads, the described process of reading the binary equivalents of the form and forming the given binary equivalents is repeated IJ-1) times and is similar to the work in the first cycle. The difference is that in the second and subsequent cycles, the counter 15 is working

only in sum1.: iru mode, and expansion1) 4 addressing and reading from the second 21 Psm unit is not performed, since the amount of shift is determined by the binary order stored on the binary order register 16 and recorded in the first cycle. The result of the conversion is removed from the adder 5 and the register 16 in binary order. Moreover, the sign of the binary order is opposite to the sign of the produced shift.

0

To reveal the technical and economic effect, it should be noted that the conversion process in the known converter is carried out in two stages. Moreover, in the first stage, the summation of the works of the converted tetrads is made to the corresponding binary equivalents, and in the second, the sum of the binary equivalents of the tetrads is multiplied by the reading from

0 of the memory block is a binary coefficient uniquely determined by the magnitude and sign of the decimal order. In the second stage, multiplication of full-digit numbers is required.

In the proposed device, multiply 5 full-digit numbers are not needed, since the memory unit stores the given binary equivalents of the form. Therefore, the gain is equal to the time spent on multiplication

0 two n bit numbers.

Claims (2)

Invention Formula five A binary fraction decimal fraction converter containing a tetrade register whose input is the information input of the converter, the first decoder, the group 0 elements And, adder, pulse generator, whose input is the trigger start input of the converter, pulse distributor, service information register, address counter, binary order register, first 5-memory block whose input is connected to the output of the address counter, tetrad register output is connected with the information input of the first decoder, the output of which is connected to the first inputs of the elements 0 And the groups whose outputs are connected to the input of the adder, the outputs of the adder are the outputs of the mantissa of the converter, the output of the pulse generator is connected to the clock input of the distribution of the body of pulses, the control input of which is the control input. converter, the first information input of the pulse distributor is connected to the first output of the service information register, the first, second O and the third inputs of which, respectively, are the input of the decimal order of the converter, the input of the sign of the order of the converter and the input of the sign of the decimal mantissa are converted to LL, the second output of the service information register is connected to the second information input of the pulse distributor and the first input of the address counter, the second input which is connected to the third output of the service information register and the third information input of the pulse distributor, the first, second, third and fourth outputs of which are connected to responsibly with the clock inputs of the tetrad register, the first decoder, the adder (and the address counter, the first output of the binary order register is the output of the converter order, characterized in that, in order to improve performance, a shifter, a second decoder, a second memory block, are entered into it The input is connected to the output of the second decoder, and the output is connected to the input of the binary order register, the second output of which is connected to the shift control inputs, the information input of which is connected to the top of the block the memory, the output of the shifter is connected to the second inputs of elements AND of the group, and the first, second and third 5 inputs of the second decoder are connected respectively to the fifth output of the pulse distributor, the second and third outputs of the service information register. 0 2. The converter according to claim 1, characterized in that in it the address counter is reversible. Sources of information taken into account in the examination 5 USSR author's certificate in application 2649587/24, cl. G06 F 5/02, 1975. 2. USSR author's certificate in reference No. 2818807/24, cl. G06 F 5/02, 08.08.79 (prototype). t1 P It l Z1 nineteen