SU1035601A2 - Multiplication device - Google Patents

Description

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O) The invention relates to k computing technology and can be used in the development of high-speed devices for multiplying the numbers represented in any positional number system in the additional code. According to the main auth. N 888109 a device for multiplying is known, containing a register of multiplicable, n blocks for calculating discharge values of a product (n is the number of multiplicable bits), n buffer registers of the first group, and n buffer registers of the second group, with the first inputs of blocks of calculating bit values the products are connected to the outputs of the corresponding bits of the register of the multiplicand, the second inputs are with the inputs of the device multiplier, the third and fourth inputs are with the outputs of the corresponding buffer registers of the first and second groups, the inputs of the first and second buffer registers The second group is connected respectively to the outputs of the high and low bits of the corresponding blocks for calculating bit values of the product, the output of the first buffer register of the second group is connected to the output of devices, the fourth input of the last block for calculating bit values, is connected to the correction input of the SP device. The disadvantage of this device is the impossibility of multiplying the numbers represented in the additional code by Him, which significantly reduces its scope. The purpose of the invention is to expand the scope of application of the device due to the possibility of multiplying the numbers in the additional code. The goal is achieved by the fact that the device for multiplying additionally contains a unit for converting a multiplier into an additional code, the information input of which is connected to the input of the multiplier of the device, the first and second control inputs with the sign of the multiplicable sign and the attribute of the additional device code, respectively, and the output with the fourth input of the last block calculating bit values of the product. In addition, the transducer into the additional code contains a counter, a register and a trigger, the output 0H of which is connected to the counting input of the counter, and the information output to the information input of the counter, the output of which is the output of the block, whose information input is connected to the information input of the counter, the overflow output of which is connected to the information input of the trigger, the installation input of which is connected to the installation input of the register and the second control input of the block, the first control input of which is connected ene to enable input register. Figure 1 shows the block diagram of the device; 2 shows a multiplier conversion block; additional code for the case of a binary-coded number system. The device contains (Fig. 1) p-bit register 1 of the multiplicable, blocks 2 for calculating the bit values of the product, buffer registers 3 and the first and second groups, respectively, block 5 of converting the multiplier into an additional code, input 6 of the multiplier of the device, inputs 7 and 8 the sign of the multiplier and the sign of the additional device code, respectively, output 9 of the device. The first input of the 1st block 2 for calculating the bit values of the product (I 1,2, ..., p) is connected to the output 10 of the 1st digit of the register 1 multiplicand, the second input to the input 6 of the device multiplier, the third input to the output i -ro buffer .register 3 of the first group, fourth input - with output i of the 4–1th buffer register k of the second group, we will accept its output 11 of the most significant bit connected to the 1st buffer register 3 of the first group, and output 12 of the lower order Yes, with Mr. buffer register second. groups. The information input of the conversion factor block 5 is additional; The target code is connected to the input 6 of the device multiplier, and its first and second control inputs are connected to the inputs 7 and 8 of the sign and the additional code of the device, respectively, the output of the conversion unit 5 of the mixer B, the additional code is connected to the fourth input of the last bit 2 These production values, the output of the first buffer register 4 of the second group is the output 9 of the device. The set of the th block 2, the computation of either the bit values of the product and the i-x buffer registers 3 and 4, can be constructively implemented as a single module 13, implemented, for example, as an integrated circuit. The inclusion in the module 13 of the corresponding register register 1 of the multi as its third buffer register ensures the uniformity of the device of multiplying numbers. The block 5 of the conversion of the multiplier to the additional code implements the sequential formation of the additional code of the multiplier, starting with the younger 1, and contains (() ig.2) K-bit binary combination counter C, K-bit register 15 and trigger 16 The trigger output 16 is connected to the counting input of counter 1, the information output of which is connected to the information input of the register. 15, the output of which is also the output of block 5, the information input of block 5, which is the input 6 of the multiplier of the device, is connected to the information input of the counter I, the overflow output of which is connected to the information input of trigger 16, the installation input of which is connected to the setup input of the register 15 and the second control input of the unit 5, which is the input 8 of the attribute of the additional device code, the first control input of the unit 5, which is also the input 7 of the sign of the multiplicand device, is connected to the permission of the input of the register 15 Block 5 Ani factor in the additional code work barely - follows. In the initial state, its register 15 is zero, and in the trigger 1b a unit is recorded (this unit is recorded through the second control input of block 5, which is also the same as the 8 sign of the additional code). Then, in each cycle of the device operation in the counter, the K-inverse binary digits of the multiplier are added to the lower digit, which arrive at its information input from the input 6 of the device multiplier {it is assumed that along this input in each clock cycle inverse binary digits multiplier), 55 is the contents of trigger 16, and get B; and, with this, the sum and transfer are written respectively to register 01 L 15 and trigger 16 (register 15 in block 5 actually plays the role of a fixed-line information delay line). 3ai, the information in register 15 is dried only if there are permissive potentials at inputs 7 and 8 of the device at the same time. The presence of the resolving potential at the input 7 of the device corresponds to a negative multiplicand, and the presence of the resolving potential by 8 means that the device multiplies the number in the additional code (otherwise it is assumed that the multiplication of numbers is performed without taking into account their signs, i.e. form). Moreover, the functions of the multiplier conversion unit 5 to the additional code can in principle be performed by the module 13 additionally entered into the device, for example, if its first input is connected to the input of the .6 multiplier; and on the second and fourth gates, to submit respectively in each tact and only in the first clock of the K-bit-two-way code 00 ... 01 provided that the multiplicable is negative (otherwise, these inputs must be supplied with zeros). This ensures the homogeneity of the multiplier at the level of identical modules 13 and may be appropriate with small k digits. Consider the operation of the multiplier for the binary-coded and numeration system, i.e. when each bit of both a multiplier and a multiplier is a set of k binary numbers. In the initial state, the buffer registers 3 and j of all modules 13, as well as the register 15 of the conversion factor multiplier 5. The additional code is reset to zero, one is recorded in the trigger 16 of block 5, and the n-bit 2nd code is stored in the register 1 of the multiplicand multiplicand (nk is a binary complementary code of the multiplicand). In each of the U1 first cycles of operation of the device, its input 6 comes in parallel to the binary bits of the multipliers, beginning with its younger bits. At the same time, in the i-th block 2 of calculating the discharge values of the product, the multiplication K of the binary bits of the multiplier arriving at its second input from the input — 6 devices — is performed, on K the binary bits of the multiplicand arriving at its first input from output 10 f-ro of the 2nd bit of register 1 multiplicand and addition to K younger bits of the resulting 2-K- - bit product, through the fourth and third inputs of block 2 respectively the lower binary bits of the product (i + 1) ro block 2, formed in the previous clock cycle and stored in buffer mode ister 4 (module 13 and K of the highest binary bits of the product i of block 2 formed in the previous clock and stored in the buffer register 3 of the 13th module 13. After this, the formed K of the lower binary bits of the i block of the 2nd block from its output 12 are written in the i-and buffer register, and the upper binary bits of the output from output 11 are in the i-and buffer register 3. Simultaneously with the formation of the bit products in blocks 2 of the device during the first AND cycles of its operation in block 5, the multiplier in additional code forms With a sequential image (in K binary bits in each clock) the additional code of the multiplier, if only multiplicable is negative, the value of which, in K binary bits enters in each clock cycle, except the first, on the fourth input of the last block 2 forming the bit values neither (in the first clock cycle, this input receives zero information, since in the initial state the register 15 of block 5 is reset). This is the most practical way to add kc to the senior bits of the product of the multiplier by the multiplier of the additional multiplier code, i.e. Correspondence is entered into the result by the sign of the POSSIBLE. I After completing the first n cycles of operation of the device, n additional cycles are performed, during which information is stored from the device with the corresponding conversion, stored in the buffer registers 3 and all modules 13. At the same time, if the multiplier is positive, then the input 6 of the device is in each A zero K-bit 016 binary code 0 ... 000 is applied to the clock cycle, if the resident is negative - a single K-bit binary code 1 ... 111K (the supply of these codes is easy to implement, producing a modified information shift in the multiplier register, t. e. the value of the sign bit multiplier is filled in when the shift is released. This makes it possible to add to and higher-order multiplications of the product of the additional factor of the multiplicand, i.e. a correction is entered into the result for the multiplier sign. The receipt of the additional multiplicand code here is based on the fact that the lower-order bits of the product of the h-discharge multiplicand by the maximum possible AND-bit number is an additional multiplicand code. The output of the 2-AND-bit product of the multiplier by the multiplier in the device is carried out for. 2VI cycles of its operation through output 9 in a parallel-serial code (according to the binary bits in each cycle). In table.1 dl. All combinations of signs of factors are cited. what is used in the device as a result correction and how it is formed in it. As can be seen from the table, the device actually uses a well-known algorithm for multiplying numbers in an additional Code with two explicit corrections. It should only be noted that if the signs of the multiplicand and multiplier are included in their higher 2-th digits (this can always be ensured, for example. For estimates of the expansion of the discharge grid of factors, then additional multiplicative and multiplication codes are used as corrections, and , ultata is automatically determined by the two most significant binary digits of the most significant 2nd digit of the product: 00 means that the product is positive, 11 determines negative, 01 indicates that a positive overflow has occurred If the signs of the multiplicand and the multiplier are not a compound. 7 are part of their higher digits, then the multiplication is exactly the same as in the previous case, with the exception of the following two circumstances: first, as corrections, not additional codes are used, but additions to the multiplicand and multipliers, i.e. additional codes without signs (additions, like additional codes, are obtained in the device automatically or in block 5 in to An additional code, or by supplying 6 units for an input to the device during and additional cycles of its operation, second, the sign of the result should be formed separately by adding a p-o module to significant periods of factors (the form of the sign for this case is not shown). Consider the principle of operation of the device for the case when I 2, K, and the signs of multiplicand and multiplier are the input to their senior 2 nd digits. Let my X multiply: -1001111, multiplier У 1 -П00111, then the product Р Х-У + 01111111001001. 8 the multiplicand device and the multiplier are presented in the additional code: Xi) n 10110001 and Ур 10011001. All the main actions performed by the device when multiplying given factors, are given in table.2. After performing four clock cycles at the output 9 of the device, the product P 0001111111001001 is formed, the two most significant binary bits of which indicate that it is positive (this product is formed by four binary bits in each clock cycle). Thus, the proposed device, with the same speed as the known one, provides for the multiplication of numbers both in the additional code and in the unsigned form, i.e. without regard to their marks. This greatly expanded its scope in comparison with the known device. Table 1

The result is not corrected.

Additional multiplier code

Additional code

+ multiplicand

Additional codes multiply and multiplier

writing information to the register 15 of block 5 is blocked by the input 7 of the device

At the input 6 of the device for n extra clock cycles are zeros.

Information is allowed to be received into register 15 of block 5 via inputs 7, 8 of the device.

To the input 6 of the device for

n additional bars come

zeros.

Reception of information in the register 15

block 3 is blocked on input

7 devices

To the input 6 of the device for

n additional bars are given

units

Allowed to receive information

to register 15 of block 5 on inputs

7.8 devices.

At the input 6 of the device during n additional cycles come

units

1011,100

01100011

 0000

0000

01100011

1011

 1001

01100011

+ 0110

+ 0111

01110000

0000

1011

1111

TPT0010T 0111 0110

10110010

T a b l i

c a

0001

100) 1001

00001001 0000 0000

1100

1111

00001111 0000 0000

00001111

Claims (3)

1. DEVICE FOR MULTIPLICATION by ed. No. 888109, characterized in that, in order to expand the scope by multiplying the numbers in the additional code, a block for converting the multiplier into an additional code is introduced into it, the information input of which is connected to the input of the device multiplier, the first and second control inputs are with the inputs of the sign multiplicative and sign of the additional device code, respectively, and the output with the fourth input of the last block for calculating the bit values of the product. 2. The device according to claim 1, wherein the unit for converting the multiplier to an additional code contains a counter, a register and a trigger, the output of which is connected to the counter input of the counter, the information output is to the information input of the register, the output of which is connected to information input of the counter, the overflow output of which is connected to the information input of the trigger, the installation input of which is connected to the installation input of the register and the second control input of the block, the first control input of which is connected to the enable input reg Istra. 3 ' τ.1 1 1035601