SU1309019A1 - Multiplying device - Google Patents

Abstract

The invention relates to computing and is a multiplier of sixteen-bit binary numbers with a sign, expressed in a direct code, can be used in high-performance computing systems of a physical experiment. The purpose of the invention — speed increase — is achieved due to the fact that in the device containing switch 1, multiplier 2i-2 ly register, summing node 3, OR 4 and AND 5 elements, firmware control block 6, consisting of programmable logic matrix 7 and register 8, trigger 9, additional switch 12, - inversion unit 13, shift node 14, adder 15, buffer register 17, additional shift node 16, accumulating adder 18 and pulse distributor 21, are multiplied by two products, orye are calculated in the multiplying operation and are numbers obtained by multiplying the multiplicand input to the input 11 "on four bits multiplier supplied to the input 10. Table 2. 2 yl. c (L z co.}

Description

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15

The invention relates to computing technology and can be used in high-performance information-computational systems created on the basis of large integral circuits used in complexes of a physical experiment and the control of fast protec- tion processes.

The purpose of the invention is to increase speed.

FIG. 1 is a functional diagram of the device; FIG. 2 is a time diagram of the operation of a multiplier pulse distributor.

The device for multiplying (Fig. 1) contains a switch 1, designed for transmitting multiplier / Y /, register 2, -24 multiplier, summing node 3, IL 4 element, AND block 5, microprogram control unit 6, which includes programmable logical matrix (HSS) 7 and micro-operations storage register 8, trigger 9, multiplier input 10, multiplicative input 11, additional switch 12, inversion unit 13, shift node 14, adder 15 additional shift node 16, buffer register 17, accumulator adder 18, which includes adder 19 and register 20, -2 04, the distributor 21 pulses the input 22 start.

Register 2 has the ability to disconnect the output of the register 2d-24 busses from its inputs by signals from the distributor of 21 pulses and is intended to overwrite the contents of one tetrad multiplier into the next.

The node 3, the trigger 9, the elements 4 and 5 are intended to form a correction of the tetrad loaded into the tetrad of the register 2 "multiplier.

A firmware control unit 6 consisting of a PLA intended for generating control signals (operation commands) and a register controlled by the distributor 21 for recording control signals (operation commands) controls the operation of the device.

five

20

2-5

thirty

J5

40

50

The relationship between the input information of the PLM 7 (tetrads) and its output information (control signals of the control unit 6 R1-R12) is given in Table. one.

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15

309019--2

Switch 1 is designed to transmit the multiplicand and is able to transfer its outputs to the zero and third state by signals R12, R1 of block 5 6. Switch 1 can be built on AND gates, the element NOT and bidirectional keys.

Adder 15 is designed to sum the input codes and is able to transfer its outputs to the third state by the signal of block 6. Controlled inverter 13 is designed to invert the multiplicand by sig6, to shift the multiplicand / X /.

Nalu R3 block 6, the node 14 is designed

., when 19 among the node 14, the shift can be constructed using three groups of switching keys (three keys per group) and

0 three groups of grounding keys. The keys are controlled by the signals R4, R5, R6 of block 6.

Accumulating adder 18 consists of adder 19, designed for

-5 the summation of the partial products recorded in registers 17 and 20 than the transfer input of the adder is not with the output of the signal R11 recorded in register 17, and the accumulator registers intended for storing the lower-order result numbers that are not involved in further operations; older 15 bit output tires and output tire

5 sign bit register 20, connected to the input tires of the second term of the adder 19 as follows. The sign bit bus from the register output 20 is connected to the sign bit input bus and four high-order input buses, the output buses of the register 20, from 1 to 15 are connected to the input buses of the second term of the adder 19, respectively, from 5 to 19, all of the output register buses - the accumulators 20, -20 are connected to the outputs of the device in accordance with the precedence of the bits of the result recorded in them.

0

The device allows you to multiply the binary sixteen-digit numbers represented in the direct code. The device allows the algorithm to perform the multiplication of two numbers X and Y, which is reduced to four cycles of summation of partial products obtained by dividing the multiplier Y into groups of 4 bits and mind 31

knitting each of the groups into a multiplicand / X /.

The algorithm for calculating partial products of the form / X / Y: is given in Table. ; 2.

The device works as follows.

Let it be necessary to calculate the product of two sixteen digit numbers X and Y, represented in a direct code with a fixed comma, and, moreover, / Y / 1.

Let X X..X

 Y YY, (f where X, Y are the sign bits of numbers

X and Y, X Y

... 16 - significant bits of numbers X and Y.

sixteen

.one "-"

sixteen

Then, Y ZY 2-

 (,)

We divide / Y /. into groups of 4 bits (tetrads), starting with the higher bits. Let tetrads be denoted by Y, 2,3,4. Obviously, the highest order of the series Y is always O,

The multiplication algorithm consists in converting the product of the moduli of the factors to obtain the result module in the forward code, the sign of the result is obtained by summing the sign digits of the factors in modulo 2.

Convert expression (1) as follows:

/X/./YHX/.I.Y. . (PG)

 / X /. (((2-UY3),) 2-% Y,

(0 + / X | .Y4) -2- + / X / .Y, 1 r

+ | Xf.Y 2- -b / X / Y, (2)

Sgn (X Y) Sgn (X) ® Sgn (Y) (3)

As can be seen from expression (2), the multiplication algorithm at each step can be represented as a sequence of the following operations: calculating the expression for the form / X / Y :; addition with the contents of the accumulator, calculated at the previous step and shifted by 4 bits to the right, recording the amount received in the accumulator.

The operation of the device is based on the fact that using a set of basic numbers from the set / X /; Yj l any partial production can be obtained

090194

maintaining / X / - YJ per cycle of addition (referring to the summing element). In tab. Figure 2 shows how you can, using the set of basis numbers 0011, 5 0101, 0111, add, shift, convert to additional code, obtain various partial products of the form / X / Yi (for all YJ combinations).

W Multiplicable / X | and the multiplier / Y / is fed to the inputs of the device.

The multiplier YJ is fed to the inputs of the register 2 -2.

The inputs of register 2, and 2 and node 3 f5 are maintained in the disconnected (third) state until the recording of the tetrads in the corresponding sections on the pulse of the distributor 21. Then for the entire conversion time, the outputs of the switch 0 of the mutator 1 are disconnected from their output buses, and the outputs of the sections 2 and 2 and node 3 are connected, respectively; but, to the inputs of the sections.

After recording the multiplier in the input 5 register multiplier younger tetrad

enters the PLM 7 input, which generates a set of control signals at the outputs that determines the mode of operation of the device at this step 0 of the calculation. This set of signals is recorded into register 8 by the pulse of the distributor 21. Each subsequent tetrad entering the register section 2 of the multiplier addresses 5 in each clock of the PLA 7 and the corresponding control signals are generated at its outputs, which are then rewritten into the & register.

Four tetrads out of 16 possible, 0 namely (Table 2) j Y (.1001; .1101; 1011, 1111) form partial products of / X / Y., which are obtained indirectly, namely, through tetrads Yj IY, t . The / X / -Y (Table 2) is represented as / X / () / X / - / X / Yj. The calculation of lagging / X / Y is as follows: at this step, formfc is the partial product / X | - Yj, expressed in 0 additional code, and the missing / X / is taken into account by adding one unit to the lowest bit of the tetrad used to obtain the partial product at the next step .

During the receipt of the command of operations addressed by the i-th notebook, one (1-1) -th unit is added to the lower order, if Yj YJ, this is 5

It is implemented using node 3. In case the extreme bits of Y, recorded in section 2, are equal to 1 (i.e. WB: at the output of element 5, a logical 1 occurs, which through element 4 enters the transfer input of node 3 and adds with notebook Y; -1, recorded in section Zj. Trigger 9 detects the presence of transfer at the output of node 3 of summation.

Since the device processes significant digits of the numbers written in the direct code, the tetrad Y, in any case, is no more than .0111 and in the case of its correction, the transfer does not occur.

The partial products are formed from the multiplier / X / on blocks 12-16 and are written to register 17 for further summation.

Claims (1)

Invention Formula A multiplier containing a multiplier register accumulating an adder, a trigger, a switch, a pulse distributor, and a shift node, the output of the accumulating adder being an output of the device, characterized in that in order to improve speed, an additional shift node and switch are entered into it , a buffer register, an adder, an inversion unit, a summation node, AND and OR elements, and a microprogrammed control unit, the input of the multiplicand device being connected to the information inputs of the auxiliary commutation ator, node of shift and block of inversion, the first output of the block of microprogram control is connected to the control input of information passing to the output of the additional switch, the output of the i-th bit of which (where, ..., 15) is The adder input is connected to the input of the shift node, the output of the additional shift node is connected to the information input of the buffer register, the output of which is connected to the information input of the accumulating adder, the input of the device multiplier is the information input of the switch, the output of which is j-ro where, ..., 16) is connected to the jth bit of the information input of the register multiplier, the write enable input of which is connected to the write enable input of the summing node, the control input of the switch, the trigger reset inputs and the accumulating adder and the first output of the pulse distributor, the second output of which is connected to the synchronous inputs of the trigger and the microprogram control unit and the input of the overwriting resolution of the multiplier register, the information input of the Kth bit of which (where, ..., 12) is connected to the output (K-4 ) - the first bit of the register of the multiplier, the outputs of the bits from the ninth to the twelfth register of the multiplier are connected to the information input of the summation node, the outputs of the bits of which are connected from the thirteenth to the sixteenth bits of the information input the multiplier multiplier whose bit outputs from the thirteenth to the sixteenth are connected to the group of inputs of the mode of the microprogram control unit; the fourth, fifth and sixth outputs of which are connected to the offset resolution inputs by two bits, one bit and the resolution input direct transfer of the shift node, the transfer output of the summation node is connected to the information input of the trigger, the output of which is connected to the first input of the OR element, dinene with information input (i + A) - the output of which is connected to the input of the bit of the additional shift node, information input of (i + 1) -ro of the discharge of which is connected to the output of the i-ro of the adder, the input of the information transmission passage of which is connected with the second output of the firmware control unit, the third output of which is connected to the control input of the inversion unit and with the first, second and third bits of the first information input of the adder, (i + 3) -and the information input of which is connected to the output of the i-ro bit yes block inver this second information 55 The summation node renos, the thirteenth and sixteenth bits of the register of the multiplier are connected respectively to the first and second inputs of the AND element, the output of which is connected to the second input of the OR element, the device start input is connected to the pulse distributor start input, the third and fourth outputs of which are connected to the inputs enable recording, respectively, of the buffer register and accumulating adder, the seventh, eighth, nine outputs of the block of the firmware control unit, ten 15 20 thirty 25, 3090196 The adder input is connected to the input of the shift node, the output of the additional shift node is connected to the information input of the buffer register, the output of which is connected to the information input of the accumulating adder, the input of the device multiplier is the information input of the switch, the output of which is j-ro where, ..., 16) is connected to the jth bit of the information input of the register multiplier, the write enable input of which is connected to the write enable input of the summing node, the control input of the switch, the trigger reset inputs and the accumulating adder and the first output of the pulse distributor, the second output of which is connected to the synchronous inputs of the trigger and the microprogram control unit and the input of the overwriting resolution of the multiplier register, the information input of the Kth bit of which (where, ..., 12) is connected to the output (K-4 ) - the first bit of the register of the multiplier, the outputs of the bits from the ninth to the twelfth register of the multiplier are connected to the information input of the summation node, the outputs of the bits of which are connected from the thirteenth to the sixteenth bits of the information input the multiplier multiplier whose bit outputs from the thirteenth to the sixteenth are connected to the group of inputs of the mode of the microprogram control unit; the fourth, fifth and sixth outputs of which are connected to the offset resolution inputs by two bits, one bit and the resolution input direct transfer of the shift node, the transfer output of the summation node is connected to the information input of the trigger, the output of which is connected to the first input of the OR element, 40 - the output of which is connected to the input ne0 five The summation node renos, the thirteenth and sixteenth bits of the register of the multiplier are connected respectively to the first and second inputs of the AND element, the output of which is connected to the second input of the OR element, the start input of the device is connected to the trigger input of the pulse distributor, the third and fourth outputs of which are connected to the enable inputs records, respectively, of the buffer register and accumulating adder, the seventh, eighth, and nine outputs of the firmware control block are connected respectively to the enable inputs shift by three, two and one bit additional node shift, the inputs of the transfer of direct and inverse codes which are connected respectively to the tenth and eleventh outputs of the microprogrammed control unit, the eleventh and twelfth outputs of which are connected respectively to the input of the sign bit of the buffer register and the control input of the additional switch, the input of the eighteenth bit of the adder is connected to the first bit of the information input of the additional shift node and the input of the logical zero of the device, the output of the sign bit of the buffer register is connected to the transfer input of the accumulating adder. Tetrad Yi Mathematical expression for calculating / X / Y; /X/.Y;.00 ... About J / X /. Yj / x / -2 / X / -YJ / X / 2 /X/-Y.(/X/ + / X / -2) / X / -YJ D / 2 / X / Y: (/ X / + / X / -2 2 / X / yj / x / .. /X/.Yj / X / - / X /. 2, / X / .Yj / X / -2- / X / -Yj /X/.(1-.0111) / X / - / X / -.0111 /X/..010l.2 / X / -Yj / X / - (1 -010O / X / - / X / -.0101 / X / Yj (/ X / ..0011) 2 " / X / Yj - (/X/.0011) + / X / / X /. Yj (X-.0111) -2 /X/.Yj(/X/-/X/.2) T a b l and c a 2i The sequence of elementary operations required to calculate / X / Y: Tire reset Shift / X / 4 bits to the right Shift / X / 3 bits to the right Addition / X / with shifted / X / by -J bit to the right, shifting the result by 3 bits to the right Shift / X / 2 bits to the right Addition / X / with shifted by: 2 bits to the right / X /, shift of the result by 2 bits to the right Obtaining a partial product /X/-.0011, shift the result by 1 bit to the right Shift / X / by 3 bits to the right, conversion to an additional code, addition with / X /, shift the result by 1 bit to the right. / Shift / X / 1 bit right Receipt, conversion to additional code, addition with / X / Receiving, shifting the result by 1 bit to the left Receive / X / .0101, conversion to additional code, addition with / X / Receive / X /. 0011, shift the result by 2 bits to the left Calculation / X / -.OOP, conversion to additional code, addition with / X / Calculation /X/.0111, shifting the result by 1 bit to the left Calculate / X / 2, shift 4 bits to the right, convert to additional code, add to / X /. Compiler N.Markelova Editor I.Tupitsa Tehred V.Kadar Proofreader M.Demchik Order 1799/41 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 cm CNJ