SU1183959A1 - Device for summing numbers - Google Patents

Abstract

A device for summing numbers containing a accumulating adder, a counter, two BAN elements and two elements AND, the outputs of the accumulating adder connected to the lower bits of the output bus of the device addition of the counter, the outputs of the bits of which are connected with the higher bits of the output bus of the device and with the output of the device sign, the direct input of the first element of the LAPT is connected with the inverse input of the second element BAN, and the inverse input of the first BAN element is connected to the direct input of the second BAN element and to the transfer output of the higher bit of the accumulating adder, the first input of the first element And is connected to the first input of the second element And, the second inputs of the first and second elements And connected to the outputs the first and second elements of the prohibition, the input of the resolution of the sum of the device is connected to the first control to the input of the accumulating adder, characterized in that, in order to expand the functionality By summing up the accumulation of products of the form ± aa b, an RS-trigger, three elements AND, a group of elements AND, the information inputs of the device connected to the first inputs of the elements AND group, the second inputs of which are connected to the first inputs of the third and the fourth elements And with the input setting the device operation mode, and the outputs are connected to the inputs of the first accumulator € adder, the input of the device sign is unified With the second input of the third element And, the output of which is connected to the direct input of the first The first element BAN and with the first input of the fifth element I, the synchronization input of the device is connected to the second input of the fourth element I, the output of which is co00 with the first input of the first element with that AND and the single input of the RS flip-flop with the second input of the first element I, the third input of which is connected to the inverse output of the digit discharge of the counter, and the output connected to the installation input of the additional discharge of the counter, the discharge outputs of the accumulating adder are connected with the corresponding informs by the counter inputs, the bit outputs of which are connected to the corresponding inputs of the second group of the accumulating adder; the output of the first discharge; the accumulator of its accumulator is connected to the information input of an additional time

Description

a row of the counter, the output of which is connected to the information input of the higher bit of the accumulating adder, i the device shift input is connected to the shift input of the accumulator and the counter summing up 1183 59 59 snoolev input RS-flip-flop.

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The invention relates to computing and can be used in specialized computing devices.

The purpose of the invention is to expand the functionality of the device due to the summation with the accumulation of works of the taibL type.

Fig, 1 shows a block diagram of the device; in fig. 2 shows an example of the implementation of a block diagram of the accumulating adder.

The device contains accumulating adder 1, counter 2, RS-flip-flop 3, prohibition elements 4 and 5 elements 6–10, group 11 11, bits of the device input bus 12, device 13 input, device sync input 14, input 15 mode settings: device operation, shift input 16, rewriting input 17, device output bus 18 lower bits, device output bus 19 high bits, device 20 sign output, high-order transfer output 21 of accumulator accumulator 1, output 22 of the first bit counter 2, output 23 additional bits counters and 2, inlet 24 resolutions Display resolution vschachi amounts device output 25 of the first discharge of the accumulator 1, the inverse output 26 sign bit counter 2,

Accumulating adder -1 contains RS-triggers 27 and 28, one-bit adders 29, elements AND 30 - 34 elements OR 35 and 36 and elements .37 - 40 delays.

The device works as follows,. g

When calculating the sum of the form 2. (± a.) Where r 2; a- - numbers, represented in parallel form by a binary additional code, at input 15

setting the device operation mode should be a single signal, and zero signals at the shift input 16 and at the rewrite input 17. In addition, each number arriving at the inputs 12 and 13 of the device is represented by n-informational and one-digit digits, and the result is m + n -informational and also one significant digit. At the same time, positive numbers are coded direct, and negative numbers are encoded with additional codes.

The device allows you to sum the arrays of numbers by algebraically adding the next (k) (n + 1) bit, including the digit of the input term entering the inputs 12 and 13 of the device, with the result of adding the previous k numbers stored in the adder 1 and the counter 2, Input terms may be positive or negative. The device, which contains m + pin bits, in the most unfavorable case (the numbers of only one sign and maximum in modulus are added) allows the addition of 2 (n + 1) -bits, including the sign bit of the input binary numbers

When summing the input p-bit of the term and being in the adder 1 mp n bits at the input, e 14 synchronization should be a zero signal, and after the end of the summation - a single signal

Let the inputs 12 and 13 of the device receive a positive number, and in the adder 1 and in the counter 2 is found a positive or negative number,

If in summing the input p-bit term and being in the adder 1, the lower n bits at the output 21 of the transfer of the most significant bit of the accumulating adder 1 are a single signal, then the output of the element BANGE 4 will also be a single signal. In this case, the single signal appearing at the synchronization input 14 after the end of the summation of the input term and located in the adder 1 of the lower order bits, through the element 6, adds one to the contents of the counter 2. In the case when summing the input n-bit the summand and the low-order bits in the adder 1 at the output 21 of the transfer of the highest-order bit to 1 of the admitting adder 1 have a zero signal, then the output of the BAN 4 will be a zero signal. In this case, the single signal appearing at the synchronization input 14 after the end of the summation of the input term and located in the accumulating adder 1 of the best n bits and bits does not change the contents of the counter 2. Let the negative number enter at the inputs 12 and 13 of the device 1 and in counter 2 it finds a positive or negative number. If, when summing the input p-bit term and being in the m3 tent 1, the lower ti bits at the output 21 of the highest-order transfer of accumulating adder 1 are zero drive, then the output of the element BAN 5 will be a single signal. In this case, a single signal appearing at the input 14 of the synchronization after the end of the summation of the input term and located in the adder of 1 lower bits, through the element And 7 subtracts one from the contents of the counter 2. In the case of the summation of the input n-bit If the second term and., located in the adder 1, the lowest n bits at the output 21 of the transfer of the most significant bit of the accumulating adder 1 are a single signal, then at the output of the element BANGE 3 there will be a zero signal. In this case, the single signal appearing at the sync synchronization input 14 after the end of the summation of the input term and being in the accumulating adder 1, the low and n bits, does not change the contents of counter 2. 59. 4 When calculating the form (+ a; b ) the inputs 12 of the device receive a multiplicand a. represented by n-information bits. In this case, if the result of the product a.b is positive, then a. It is encoded with a direct code, and if the result is a negative result, then a is encoded with an additional code. At the same time, a product mark arrives at the input bus 13 of the device symbol. B., And the input of setting the device's operation mode without a sign bit is received by the binary number b-, represented by the (t - 1) -disable direct sequential position code, starting with the least significant bits. The sum () is represented by I + n informational and one significant bits. Before the start of tajb multiplication, the extra bit in counter 2 is in zero state. If the first least significant bit of the number b .; equal to one, then the input number a. and the mark of the product a-b. About ° P the corresponding group of elements And 11 and the element And 8 both go to the corresponding; and the inputs of accumulating adder 1, the elements BANCH 4 and 5, the element AND 10. If the significant bit of the result RSgr is in the zero state (positive number) , and at the input 13 of the device sign, and consequently, at the output of the AND 8 element there is a single signal (the product sign a is –B negative), then only in this case, at the output of the AND 10 element will there be a single signal that will establish an additional bit counter 2 in one state. The summation processes in accumulative adder 1 are performed in the same way as when calculating the sum g% view (± aj). Here, a single signal appearing at sync input 14 after the end of the summation of the input term a. and on 1 lower bits going through the accumulating adder, passes through AND 9 element. This single signal from the output of AND 9 element sets RS-flip-flop 3 to one state, and also adds one to counter 2 or subtracts one from counter 2, also as when performing a function of the form (+ a;). Then a single signal arrives at the shift input 16.

which shifts the result found in accumulator 1 and counter 2 by one bit to the left, with the least significant bit in accumulator 1, being overwritten by the additional digit of counter 2,

In the event that the first least significant digit of the number is zero, then only a single signal arriving at the input 16 of the shift shifts the result found in the accumulator of adder 1 and counter 2 by one bit to the left

Upon receipt of the subsequent bits of the number b. the device works as described

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After the last digit of the number b. A single signal is received at rewriting input 17, which 5 rewrites the result in accumulator adder 1 and counter 2 so that in accumulator adder 1 the lower bits 10 of the result will be in the corresponding sequence, and in the counter 2 the most significant and sign bits of the result. In this case, a single signal arriving at rewriting input 17 sets the additional bit of counter 2 to the zero state.

As a result, the product ± a b - will be added to the contents of the glowing adder 1 and counter 2.

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19,20,23

Claims (1)

DEVICE FOR SUMMING NUMBERS, containing an accumulating adder, a counter, two elements BAN and two elements AND, with the outputs of the accumulating adder connected to the least significant bits of the output bus of the device, the output of the first element And connected to the subtraction input of the counter, and the output of the second element And connected to the input of addition counter, the outputs of the discharges of which are connected to the high-order bits of the output bus. of the device and with the output of the device sign, the direct input of the first element 'FORBID is connected to the inverse input of the second element and the inverse input of the first element is PROHIBITED is connected to the direct input of the second element is FORBID and to the transfer output of the highest order of the accumulating adder, the first input of the first element And is connected to the first input of the second element And, the second inputs of the first and second elements And are connected respectively to the outputs of the first and second elements FORBID, the permission input for issuing the sum of the device is connected to the first control input of the accumulating adder, characterized in that in order to expand the functionality of the device due to performing summation with the accumulation of works of the form + a ₂ -b £, an RS-trigger, three AND elements, a group of AND elements are introduced into it, and the information inputs of the device are connected to the first inputs of the elements AND groups, the second inputs of which are connected to the first inputs of the third and fourth element And with the input of the job mode of operation of the device, and the outputs are connected to the inputs of the first group of the accumulating adder, the input of the device sign is connected to the second input of the third element And, the output of which is connected to the direct input of the first element is FORBID and to the first input of the fifth element And, the synchronization input of the device connected to the second input of the fourth element And, the output of which is connected to the first input of the first element And and with a single input of the RS-trigger, the inverse output of the RS-trigger is connected to the second input of the fifth element And, the third input which connected to the inverse output of the sign discharge of the counter, and the output is connected to the input of the installation of an additional discharge of the counter, the outputs of the discharges of the accumulating adder are connected to the corresponding information inputs of the counter, the outputs of the discharges of which are connected to the corresponding inputs of the second group of the accumulating adder ^ the output of the first discharge of the accumulating adder is connected to information input of an additional time 1183959 'of the counter row, the output of which is connected to the information input of the senior discharge • “shift input of the device is connected to the shift input of the accumulating torus and counter, the overwrite input of the device is connected to the corresponding second control input of the accumulating adder and the control input of the counter, and also to the zero input of the RS-trigger