SU1270757A1

SU1270757A1 - Device for taking sum of binary numbers

Info

Publication number: SU1270757A1
Application number: SU853901950A
Authority: SU
Inventors: Михаил Алексеевич Дуда; Збышек Иванович Домбровский; Василий Николаевич Немиш; Людмила Анатольевна Узлова
Original assignee: Тернопольский Финансово-Экономический Институт
Priority date: 1985-05-27
Filing date: 1985-05-27
Publication date: 1986-11-15

Abstract

. Изобретениеотноситс к автоматике и вычислительной технике. Цель изобретени - расширение области применени устройства за счет обеспечени возможности суммировани чисел и представлени результата сум- мироиани как в обратном, так и в дополнительном зсодах. Устройство дл суммировани двоичных чисел содержит накапливающий сумматор, причем входна шина знака устройства соединена с входом знака накапливающего сумматора , а вход разрешени суммировани устройства соединен с входом разрешени накапливающего сумматора. Новым в устройстве вл етс введение параллельного сумматора, шести элементов И, двух элементов ЗАПРЕТ, трех элементов ИЛИ, одного элемента i И-НЕ и одного элемента НЕ, которые соответствующим образом соединены сл между собой, с входными шинами устс: ройства и с входами и выходами на .капливающего сумматора. 2 ил.. The invention relates to automation and computing. The purpose of the invention is to expand the field of application of the device by providing the possibility of summing up the numbers and presenting the result of the summation both in the reverse and in the additional result. The device for summing binary numbers contains an accumulator adder, the input bus of the device sign connected to the sign input of the accumulating adder, and the enable input of the summation of the device connected to the permission input of the accumulating adder. A new device is the introduction of a parallel adder, six AND elements, two BANNER elements, three OR elements, one AND-NOT element, and one NOT element, which are interconnected appropriately with each other, with device input buses: devices and with inputs and outputs to the accumulator. 2 Il.

Description

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Изобретение относитс к автоматике и вычислительной технике и может быть использовано, в частности, при реализации арифметических устройств специализированных цифровых вычислительных машин.The invention relates to automation and computing and can be used, in particular, in the implementation of the arithmetic devices of specialized digital computers.

Целью изобретени чл етс расширение области применени устройства за счет обеспечени возможности суммировани чисел и представлени результата суммировани как в обратном , так и в дополнительном кодах.The aim of the invention is to expand the field of application of the device by providing the possibility of summation of numbers and the presentation of the result of summation in the reverse, and in additional codes.

На фиг. 1 представлена блок-схема устройства дл суммировани двоичных чисел; на фиг. 2 - блок-схема параллельного сумматора.FIG. 1 is a block diagram of an apparatus for adding binary numbers; in fig. 2 is a block diagram of a parallel adder.

Устройство дл суммировани двоичных чисел (фиг. 1) содержит накапливающий сумматор 1, параллельный сумматор 2, элементы И 3-8, ЕПИ 9, 10 и 11, И-НЕ 12, НЕ 13, ЗАПРЕТ 14, 15, входную числовую шнну 16 и входную шину 17 знака слагаемого, вход 18 разрешени суммировани , входы 19, 20 и 21 задани режима, выход 22 переноса, выход 23 знака и входThe device for summing binary numbers (Fig. 1) contains accumulative adder 1, parallel adder 2, elements AND 3-8, EPI 9, 10 and 11, AND-NO 12, NOT 13, BAN 14, 15, input numeric string 16 and the input bus 17 of the term sign, the input 18 of the summation resolution, the inputs 19, 20 and 21 of the mode setting, the output 22 of the transfer, the output 23 of the character and the input

24переноса младшего разр да накапливающего сумматора 1, выходную шину24 low-order transfer of accumulating adder 1, output bus

25параллельного сумматора 2. Параллельный сумматор 2 содержит25 parallel adder 2. Parallel adder 2 contains

последовательно соединенные сумматоры 26-29.series-connected adders 26-29.

Устройство дл суммировани двоичных чисел работает следующим образомThe device for summing binary numbers works as follows.

Число А , поступающее на соответствующие входы 16 и 17 устройства, и число В , хран щеес в накапливающем сумматоре 1, представлены п числовыми и двум знаковьми разр дами, а результат. суммировани С , образующийс и хран щийс в накап-ливающем сумматоре 1, представлен такжеп числовыми и двум знаковыми разр дами . При этом, если число / , поступающее на входы 16 и 17, представлено в дополнительном модифиц;ированном коде, то на входе 20 задани режима устройства должен быть нулевой сигнал, а если число Д представлено в обратном модифицированном коде, т(5 на входе 20 задани режима устройства должен быть единичный сигнал. Аналогично, если число & , хран щеес в накапливающем сумматоре 1, представлено в дополнительном модифицированном коде, то на входе 19 задани режима устройства дол;кен быть единичньй сигнал. Если же результат суммировани С должен быть представлен в дополнительном модифицированном коде, то на входе 21 задани режима устройства долженThe number A arriving at the corresponding inputs 16 and 17 of the device, and the number B stored in accumulator 1, are represented by n numeric and two sign bits, and the result. summation C, which is formed and stored in accumulator 1, is also represented by numeric and two significant digits. At the same time, if the number / arriving at inputs 16 and 17 is represented in an additional modified code, then the input 20 of the device mode setting must have a zero signal, and if the number D is presented in a reverse modified code, t (5 at input 20 the device mode must have a single signal. Similarly, if the number & stored in accumulator 1 is presented in an additional modified code, then the device signal must have a single signal at input 19; if the result of C is redstavlen additional modified code, the inlet device 21 specifying mode must

быть нулевой сигнал, а если результат суммировани С должен быть представлен в обратном модифицированном коде, то на входе 21 задани режима устройства должен быть единичныйthere should be a zero signal, and if the result of the summation C is to be represented in the reverse modified code, then the input 21 of the device mode setting must be one

сигнал.signal.

Пусть числа Д и 6 представлены в дополнительных модифицированных кодах, а результат С суммировани должен быть представлен в дополнительном модифицированном коде. В этом случае на входах 19, 20 и 21 задани режима устройства будут нулевые сигналы, вследствие чего на выходах элементов И 3-8, ЗАПРЕТ 14Let the numbers D and 6 be represented in additional modified codes, and the result C of the summation should be presented in an additional modified code. In this case, the inputs 19, 20, and 21 of the device mode settings will have zero signals, as a result, at the outputs of the elements AND 3-8, BAN 14

и 15, ИЛИ 9 10 к 11 будут нулевые сигналы, а на выходах элементов И-НЕ 12, НЕ 13 - единичные сигналы. При этом независимо от знаков чисел / и В на выходе параллельного сумматора 2 будет результат суммировани . числовой части числа А с числом 0...0. При поступлении сигнала на вход 18 разрешени суммировани з накапливающем сумматоре 1 будет осуществл тьс суммирование числа 8 , хран щегос в накапливающем сумматоре 1 , с числом,числова часть которого сформирована на выходе параллельного сумматора 2, а знак тот же, что иand 15, OR 9 10 to 11 there will be zero signals, and at the outputs of the elements AND-NO 12, NOT 13 - single signals. In this case, regardless of the signs of the numbers / and B, the output of the parallel adder 2 will be the result of the summation. the numeric part of the number A with the number 0 ... 0. When a signal arrives at the input 18 of the resolution of the summation from accumulating adder 1, the number 8 stored in accumulating adder 1 with the number whose numerical part is formed at the output of parallel adder 2 is summed, and the sign is the same as

у числа А . При этом на входе 24 переноса младшего разр да накапливающего сумматора 1 всегда будет нулевой сигнал. В итоге в накапливающем сумматоре 1 будет в дополнительномat number A. In this case, at the input 24 of the transfer of the lower bit of the accumulating adder 1 there will always be a zero signal. As a result, the accumulating adder 1 will be in the additional

коде результат С суммировани чисел / и & .The result code C is the sum of the numbers / and & .

Пусть числа Д и 6 представлены , в дополнительных модифицированных кодах , а результат С суммировани должен быть представлен в обратном модифицированном коде. В этом случае на входах 19 и 20 задани режима устройства будут нулевые сигналы, а на входе 21 задани режима устройства будет единичный сигнал. ПриLet the numbers D and 6 be represented, in additional modified codes, and the result C of the summation should be presented in the reverse modified code. In this case, the inputs 19 and 20 of the device mode will be zero signals, and the input 21 of the device mode will be a single signal. With

этом на выходах элементов И 3, 4 и 7, НЕ 13 будут нулевые сигналы, а на выходе элемента ИЛИ 9 будет единичный сигнал.This at the outputs of the elements And 3, 4 and 7, NOT 13 will be zero signals, and the output of the element OR 9 will be a single signal.

Если числа Д и 6 положительные, то на выходах элементов И 5, 6, а . следовательно, и на выходах элемен ,тов ЗАПРЕТ 14, 15, ИЛИ 10 и 11 будут нулевые сигналы. При этом на .выходе элемента И-НЕ 12 будет единичный сигнал, а на вькоде параллельного сумматора 2 будет результат суммировани числовой части числа А с числом 0...0.If the numbers D and 6 are positive, then the outputs of the elements And 5, 6, and. consequently, at the outputs of the elements, BAN 14, 15, OR 10 and 11 will be zero signals. In this case, on the output of the NAND 12 element there will be a single signal, and on the code of the parallel adder 2 there will be the result of the summation of the numeric part of the number A with the number 0 ... 0.

В случае, если числа Д и 8 отрицательные , то на выходах элементов И 5, 6, а следовательно, и на выходах элементов ЗАПРЕТ 14, 15, ИЛИ 10, 11 будут единичные сигналы. При этом на выходе элемента И-НЕ 12 будет нулевой сигнал, а на выходе параллельного сумматора 2 будет результат суммировани числовой части числа А с числом 1... 1.If the numbers D and 8 are negative, then at the outputs of the elements And 5, 6, and consequently, at the outputs of the elements BANE 14, 15, OR 10, 11 there will be single signals. In this case, the output of the NAND 12 element will be a zero signal, and the output of the parallel adder 2 will be the result of the summation of the numeric part of the number A with the number 1 ... 1.

Если число Д положительное, а число ft отрицательное, то на выходе элемента И 5, а следовательно, и на выходе элемента ЗАПРЕТ 14 будет еди ичный сигнал; При этом на выходе параллельного сумматора 2 будет результат суммировани числовой части числа Д с числом 1...1. В этом случае на выходе элемента И-НЕ 12 будет единичный сигнал, так как на выходе элемента И 6, а следовательно, и на выходе элемента ЗАПРЕТ 15 есть нулевой сигнал.If the number D is positive, and the number ft is negative, then at the output of the element I 5, and consequently, at the output of the element BANE 14 there will be a single signal; In this case, the output of the parallel adder 2 will be the result of the summation of the numerical part of the number D with the number 1 ... 1. In this case, the output of the element AND-NO 12 will be a single signal, since the output of the element And 6, and hence the output of the element BAN 15, is a zero signal.

В случае, если число А отрицательное , а число Ь положительное, то на выходе элемента И 6, а следовательно , и на выходе элемента ЗАПРЕТ 15 будет единичный сигнал. При этом на выходе параллельного сум матора 2 будет результат суммировани числовой части числа Д с числом 1... 1 .В этом случае на выходе элемента И-НЕ 12 будет единичньй сигнал,так как на выходе элемента И 5, а следовательно , и на выходе элемента ЗАПРЕТ 14 есть нулевой сигнал.If the number A is negative, and the number b is positive, then at the output of the element I 6, and hence at the output of the element BAN 15, there will be a single signal. In this case, the output of the parallel summator 2 will be the result of the summation of the numerical part of the number D with the number 1 ... 1. In this case, the output of the element AND-NO 12 will be a single signal, since the output of the element is And 5, and hence, The output of the element BAN 14 is a zero signal.

При поступлении сигнала на вход 18 разрешени суммировани в накапливающем сумматоре 1 будет осуществл тьс суммирование числа В , хран щегос в накапливающем сумматоре с числом, числова часть которого сформирована на выходе параллельного сумматора 2, а.знак тот же, что и у числа Д . При этом единичный сигнал на входе 24 переноса младшего разр да накапливающего сумматора 1 есть только в том случае, если на выходе 22 переноса накапливающего сумматора 1 и на выходах элементов ИЛИ 9, И-НЕ 12 есть единичные сигналы . В итоге в накапливающем сумматоре 1 будет в обратном коде результат С суммировани чисел X и ВWhen a signal arrives at the input 18 of the summation resolution in accumulating adder 1, the number B stored in the accumulating adder with the number whose number part is formed at the output of the parallel adder 2 will be summed up, and the sign is the same as the D number. In this case, a single signal at the input 24 of the transfer of the least significant bit of accumulating adder 1 is only if at the output 22 of the transfer of accumulating adder 1 and at the outputs of the elements OR 9, AND-NO 12 there are single signals. As a result, in the accumulating adder 1, in the reverse code, the result C will be the summation of the numbers X and B

Пусть число Д представлено в обратном модифицированном коде, число В - в- дополнительном модифицированном коде, а результат С суммировани должен быть сформирован в дополнительном модифицированном коде. В этом случае на входах 19 и 21 задани режима устройства будут нулевые сигналы, а на в.оде 20 задани режима устройства будет единичньй сигнал. При этом на выходах элементов И 5, 6, 3, 7, ЗАПРЕТ 14, 15, ИЛИ 9, 11 будут нулевые сигналы а на выходах элементов И-НЕ 12., НЕ 13 будут единичные сигналы.Let the number D be represented in the inverse modified code, the number B in the additional modified code, and the result C of the summation should be formed in the additional modified code. In this case, the inputs 19 and 21 of the device mode settings will have zero signals, and on the 20 mode settings of the device mode there will be a single signal. At the same time, at the outputs of the elements And 5, 6, 3, 7, BAN, 14, 15, OR 9, 11 there will be zero signals and at the outputs of the elements AND-NOT 12., NOT 13 there will be single signals.

Если число А положительное, а число В положительное или отрицателное , то на выходах элементов И 4, ИЛИ 10 также будут нулевые сигналы. При этом на выходе параллельного сумматора 2 будет результат суммировани числовой части числа А с числом О... О.If the number A is positive and the number B is positive or negative, then the outputs of the elements AND 4, OR 10 will also be zero signals. At the same time, the output of the parallel adder 2 will be the result of summing the numerical part of the number A with the number O ... O.

В случае, если число А отрицателное , а число & положительное или отрицательное, то на выходах элементов И 4, ИЛИ 10 будут единичные сигналы . При этом на выходе параллельного сумматора 2 будет результат суммировани числовой части числа Д с числом 0...01.If the number A is negative and the number & positive or negative, then the outputs of the elements AND 4, OR 10 will be single signals. In this case, the output of the parallel adder 2 will be the result of the summation of the numerical part of the number D with the number 0 ... 01.

При поступлении сигнала на вход 16 разрешени суммировани в накапливающем сумматоре 1 будет осуществл тьс суммирование числа 8 , хран щегос в накапливающем сумматоре с числом, числова часть которого сформирована на выходе параллельног сумматора 2, а знак тот же, что и в числе А . При этом на входе 24 переноса младшего разр да накапливающего сумматора 1 всегда будет нулевой сигнал. В итоге в накапливающем сумматоре 1 будет в дополнительном коде результат С суммировани чисел Д и В .When a signal arrives at the input 16 of the summation resolution in accumulating adder 1, the number 8 stored in the accumulating adder with the number whose numerical part is formed at the output of parallel adder 2 and the sign is the same as in the number A will be performed. In this case, at the input 24 of the transfer of the lower bit of the accumulating adder 1 there will always be a zero signal. As a result, in the accumulating adder 1, the result C in the additional code will be the summation of the numbers D and B.

Claims

Let the number A be represented in the inverse modified code, the number B in the additional modified code, and the result C of the summation should be formed in the reverse modified code. In this case, the inputs 20 and 21 of the device mode settings will be single signals, and the input 19 will be a zero signal. In this case, the outputs of the elements And 3, 4, 7, NOT 13, BAN 15 will be zero signals, and the outputs of the elements OR 9, AND-FiE 12 will be single signals. If the number 6 is negative, and the number D is positive or negative, then at the output of the element And 5, and consequently, at the outputs of the elements of the prohibition ban 14, or 10, 11 there will be single signals. In this case, at the output of the parallel adder 2, the result of the summation of the numerical part of the number with the number 1 ... 1. In case the number is positive and the number D is positive or negative, then at the output of the element 5 and therefore, the outputs of the elements of the banned 14, or 10, 11, will be zero signals. In this case, at the output of the parallel adder 2, the result will be the summation of the numeric part of the number with the number 0 ... 0. When a signal arrives at the input 18 of the summation resolution in accumulating adder 1, the number 6 stored in the accumulating adder with the number whose numerical part is formed at the output of parallel adder 2 and the sign is the same as the number will be added. In this case, a single signal at the input 24 of the transfer of the least significant bit of the accumulating adder 1 is only in the case e: if at the output 22 of the transfer of the accumulating adder 1 and the elements OR 9, AND-NO 12 have single signals. ) 3 results in the accumulating adder 1 will be in the reverse code, the result C is the sum of the numbers D and B. Let the number A be represented in the additional modified code, the number fc in the reverse modified code, and the result C of the summation should be formed in the additional modified code. In this case, at the inputs 20 and 21, the device mode assignments will be zero s; ignals, and at the input 19, the device mode settings will be a single signal. In this case, the outputs of the elements And 5, 6, 4, 7, BAN, 14, 15, OR 9, 11 will be zero signals, and the outputs of the elements AND-NOT 12, NOT 13 will be single signals. If the number & is positive, and the number 4 is positive or negative, then the outputs of the And 3 and OR 10 elements will also have zero signals. In this case, the output of the parallel adder 2 will be the result of the summation of the numerical part of the number L with the number 0 ... 0. If the number B is negative and the output A is positive or negative, then at the outputs of the elements AND C, OR 10 there will be single signals. In this case, on the output of the parallel adder 2 there will be the result of the summation of the numerical part of the number A with the number 0 ... 01. When a signal arrives at the input 18 of the summation resolution in accumulating adder 1, the number B stored in accumulating adder 1 will be summed up with the number whose numerical part is formed at the output of the parallel adder 2, and the sign is the same as the number. In this case, at the input 24 of the transfer of the lower bit of the accumulating adder 1 there will always be a zero signal. As a result, in the accumulating adder 1, the result C in the additional code will be the summation of the numbers D and B. Let the number be represented in the additional modified code, the number B in the inverse modified code, and the result C of the summation up to be formed in the inverse modified code. In this case, the inputs 19 and 21 of the device mode settings will be single signals, and the input 20 will be a zero signal. At the same time at the outputs of the elements OR 9, AND-NOT 12-single signals. If number A is negative and number & positive or negative, then at the output of the element And 6, and consequently, at the outputs of the elements of the Prohibition 15, OR 10, 11 there will be single signals. In this case, the output of the parallel adder 2 will be the result of the summation of the numerical part of the number 4 with the number 1 ... 1. In case the number is positive and the number B is positive or negative, then the output of the element is And 6, and therefore the outputs the elements of the prohibition 15, OR 10, 11 will be zero signals. In this case, the output of the parallel adder 2 will result in the summation of the numeric part of the number A with the numbers 0 ... 0. 7 When a signal arrives at the input 18 of the summation resolution in accumulative adder 1, the number B stored in accumulative adder 1 will be summed, with a number whose number part is formed at the output of parallel adder 2, and the sign is the same as the number /, at the same time, the signal at the input 24 of the transfer of the lower bit of the accumulating adder 1 is only if at the output 22 of the transfer of the accumulating adder 1 and at the outputs of the elements OR 9, AND-NOT 12 there are single signals. As a result, in the accumulating adder 2 1 there will be in the reverse code the result C of the summation of numbers and В. The path of the number and are presented in the inverse modified codes, and the result C of the summation must be formed in the additional modified code. In this case, the device mode inputs will be single signals at inputs 19 and 20, and the signal at the device mode input 21 will be a zero signal. In this case, the outputs of the elements of the banned 14, 15, OR 11 will be zero signals, and on the codes of the elements IS NOT 12, NOT 13 there will be single signals. If the numbers and P are positive, the outputs of the elements And 3, 4, 7, OR 9, 10 will be zero signals. In this case, the output of the parallel sumat 2 will be the result of the summation of the numerical part of the number A with the number 0 ... 0. If the numbers and b are negative, then at the outputs of the elements OF, 4, 7, OR 9, 10 there will be single signals. In this case, the output of the parallel adder 2 will be the result of the summation of the numerical part of the number L with the number O ... 01. If the number A is positive and the number B is negative, then the output of the AND 3 and OR 10 elements will be single signals, and at the outputs of the AND elements 4, OR 9 there will be zero signals. At the output of the parallel adder 2 there will be the result of summing the numerical part of the number A with the number O ... 01. if the number D is negative and the number b is positive, then the outputs of the elements 4, OR 10 there will be 57 single signals, and at the outputs of the elements IZ, 7, OR 9 will be give zero signals. At the same time, regardless of the signs of the numbers A k, the output of the parallel adder 2 will result in the summation of the numerical part of the number A with the number O ... 01. When the signal arrives at the input 18 of the add resolution, the accumulative adder 1 will accumulate the number 6 stored in accumulating adder 1, with a number, the numerical part of which is formed at the output of the parallel adder 2, and the sign is the same as that of the number A. In this case, a single signal at the input 24 of the transfer of the least significant bit of accumulating adder 1 is only if at the output 22 of the transfer of accumulating adder 1 and at the outputs of the elements OR 9, AND-NO 12 there are single signals. As a result, in the accumulating adder 1 there will be in the additional code the result C of the summation of the numbers L and c. Let the numbers 1 and 6 be represented in reverse modified codes, and the result C of the summation should be formed in the reverse modified code. In this case, the inputs 19, 20, and 21 of the device mode assignments will contain single signals. In this case, the outputs of the elements of the banned 14, 15, OR 10, 11, and 3, 4, 7, NOT 13 will be zero signals, and the outputs of the elements OR 9, AND-NO 12 will be single signals. In this case, the output of the parallel adder 2: will be the result of the summation of the numerical part of the number L with the number 0 ... 0. When a signal arrives at the input 18 of the summation resolution in accumulating adder 1, the number stored in accumulating adder 1 with the number whose numerical part is formed at the output of parallel adder 2 and the sign is the same as is accumulated. and the number L. In this case, a single signal at the input 24 of the transfer of the least significant bit of accumulating adder 1 is only if at the output 22 of the transfer of accumulating adder 1 and at the outputs of the elements OR 9, AND-NO 12 there are single signals. As a result, in the accumulating adder 1, in the reverse code, the result C of the summation of the numbers / 4 and & . The invention The device for adding binary numbers, containing the first, second, third, fourth, fifth, sixth elements AND, first, second, third elements OR, accumulating adder and element NOT, and the sign of the operand of the device connected to the first inputs of the first and second AND elements, the first input of the third element AND is connected to the output of the element NOT, the output of the first element AND is connected to the first input of the fourth element AND, the output of which is connected to the first input of the first element OR, characterized in that Ensuring functionality by providing the possibility of summing numbers and presenting the result of the summation in both the reverse and additional codes, a parallel adder, the first and second BAN elements, the NAND element are entered into it, the first operand input of the device is connected to the first information input parallel accumulator, the second information input of which, except the input of the first digit, is connected to the output of the second element OR, the first digit of the second information input of the parallel adder It is connected to the output of the third OR element, the first input of which is connected to the first inputs of the second OR element, the NAND element and the output of the first BAN element, the direct input of which is connected to the output of the second And element, 1 5710 first the input of the device mode setting is connected to the inverse input of the second element BANGE and the second input of the third element I, the third input of which is connected to the first input of the fifth element I and the output of the sign of the result of the accumulating adder, the transfer output of which is connected to the first input of the sixth element The AND is the output of which is connected to the transfer input of the accumulating adder, the addition resolution input of which is connected to the device addition enable input, the second input of the device mode setting is connected to the inverse input of the first BAN element and the second input of the first AND element, the third input of which is NOT connected whose input is connected to the third input of setting the device mode, the second inputs of the second and fifth elements AND, and the first element OR, the output of the fifth element AND is connected to the direct input of the second BAN element, the output of which is connected to the second inputs of the second and third OR elements and the NAND element, the output of which is connected to the second input of the sixth AND element, the third input of which is connected to the output of the first, OR element, the output of the first AND element to the third input of the second the OR element, the fourth input of which is connected to the second input of the fourth and output, the third element AND, the input sign of the operand device is connected to the input of the sign bit accumulating adder, the inputs of the significant bits of which are connected with the outputs of the parallel adder.

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