SU1569825A1 - Device for dividing binary numbers - Google Patents

Abstract

The invention relates to computing and can be used autonomously or as part of a computing system to increase computation performance. The aim of the invention is to extend the functionality by dividing the numbers represented in the additional code. New in the device, containing N N-bit parallel adders and N N-bit modulo-two adders, is the introduction of N EXCLUSIVE OR elements, two NOT elements and a private digitizer. This makes it possible to organize the structure of the device, convenient for use as a high-speed special processor in the composition of computing systems, and implement it in the form of a large integrated circuit. 1 hp f-ly, 1 ill.

Description

The invention relates to computing and can be used autonomously or as part of multiprocessor computing systems to increase computational performance.

The purpose of the invention is to expand the functionality of the device by dividing the numbers n inserted in the additional code.

The drawing shows a diagram of the device for the case.

The device contains four five-bit parallel adders 1., - 15-4, -4, four five-bit adders 5 ,, - S j. - 8, -8. modulo two, a group of four elements EXCLUSIVE OR 9, -9, two elements NOT 10

and 11 and block 12 for the formation of quotients of the quotient, which consists of two groups of four adders,. modulo two in each, and a group of three elements And 15, -153.

The device works as follows.

The input of the device receives a dividend a, represented by the significant digit Zn and bits a% a2,. .., ae, and the divisor b, represented by the symbolic discharge of Zn and bits, b3 and b. The output of the device is private

but.

 represented by sign rank

D

Znh and bit x, x2, x3, x. The computation of the quotient, where the divisible and

K5

Q7

The letter b is presented in an additional code; it is executed as follows.

I

The first parallel adder calculates a slip of 6, in accordance with the expression

{a-2 b, if,. (a + 2 b, if,

where ® zn.

I The value of the first (senior) bit private x1 is calculated as

xr (© Zn © r

i

I

p is the transfer value from the high bit of the first parallel adder; r - binary variable, the value of which is calculated by the recurrent expression

city (p2 Ј) Zn) g ,.

| f W - ™ -T / J.Ј.

On the i-th parallel adder (i 2,3, ..., p), the nonexpert вычис is calculated; according to the expression

At the output of the element 10., and respectively at the second inputs of the adder 5 1 logical O and, therefore, the value of 20 divider bits goes without inversion to the second inputs of single-bit adders. At the second entrance, the size enters the Sign. The first inputs of bit 1, - 1S receive the code 10000. To the input of bit 1, the value goes

3. cr

The adder 14-15 produces a summation

)

10000 - code at the first inputs of bits 1, -15

C: t

2Ј-, if p -1 © Zn 1;

-

2Ј.i, if р1М © ЗНЬ 0. The value of the 1st bit of the quotient is calculated as

 © Zn © g; ; (, 3, ..., p),

where r; (ph З zn) g. Example. Let the divisible a and the divisor b are represented in the additional code and be equal

 a2aeafa5a6a7a8 0.10001111; Bbl3l 1.0011. 5 At the exit of element 9, receive the sign of quotient ©.

At the output of the element 10., and respectively at the second inputs of the adder 5 1 logical O and, therefore, the values of the divider bits go without inversion to the second inputs of the one-bit adders. To the second input of the bit, the value of Zn is supplied. The first inputs of bits 1, - 1S receive the code 10000. The input of the transfer of discharge 1 is the value

3. cr

The adder 14-15 produces a summation

10011 - code on the second + 1 - value a, 100100 - code at the output of bits 1 ,, - 15.

At the output of bits 1, -15, the magnitude of the gap Ј, 00100 appears. At the output of the higher-order transfer 1 (is the transfer value. The value of p 1 is fed to the input of the adder 13 modulo two, the output of which forms the value of p1, fed to the second input of the element 9if to the second inputs of the adders 6 and to the first input of yes 25 parallel adder.

Thus, the first inputs of the bit are supplied with a constant 6,

01000 - code at the first inputs of bits +

10011 - code on the second inputs of bits + 1 - value ab

11100 - code at the output of bits.

Thus, Ј2 11,100; . The transfer value p2 0 arrives at

inputs of bits 1, -lj

structurally shifted by one bit towards the higher bits (which is equivalent to multiplying by 2) - code 0100. The second inputs of the bits receive divider bits, shifted structurally by one bit towards the lower bits (which is equivalent to multiplying by) - code 10011. The value of a 1 is input to the transfer input of the 2S bit.

At the output of the adder, the magnitude of the E & and the transfer of p2 from the older bit 2:

adder 13Z input modulo two, ng the output of which is formed by the value

p2 ®. The values of the bits of the divider Zn. L (L2L3FF 1.0011 is inverted - on element 93 and adder 7. The code 01100 is sent to the second inputs of the bits of the adder. To the first inputs

11001 - code on the first inputs of bits +

01100 - code on the second inputs of bits + 1 - value at

100110 - code at the output of bits 3, -H.

Thus, $ 00110. The value of p3 1 is fed to the input of the adder 13 modulo two, where the value of p3 b is formed, which is fed to the second input of the element 9 / ±, the second inputs of the adder 8 and to the first input of the bit b5. At the first entrances of bits

01100 - code at the first inputs of bits 4, -4

10011 - code at the second inputs of bits 4, -4s; + 1 - value ah

100000 is the code at the output of bits 4h-45.

Thus, 00,000; . the value of p 1 is fed to the input of the sum- and-13 modulo two, where p р is formed, the incoming s-ha input of the adder 14 is modulo two. At the output of the adder 14, a minor discharge of the private

. 4 © Zn.

. At the output of the element-15 form-a-. with the value of a binary variable

 . G3 (Zn).

Belkin r3 is fed to the first input of the adder 143 modulo two at the output of which is formed the value of the discharge x3

© Zn.

At the output of the element And 152 the value is formed

r (p3 @ zn).

Similarly, at the output of the adder 14.g modulo two, the value of © ЗНЬ +

at the output of the element And 15, -

 © Zn), at the output of the adder 14, modulo two value of the highest bit of the private (© Zn © r, 0.

the discharge value arrives, at the first input of discharge 3 the value p2..

The adder 5 forms the 53 and transfer p3 gap values:

41-4h bits of the value code 0110 are received. The second inputs of the bits are the non-inverted values of the bits of the divider Zyom b2b3. Sum-matrix, j- forms values of non-visibility Ј, to transfer p4:

five

Thus, the values of 30 bits of the private x are obtained:

Знх х х2х3х4 1.0101.

0

Claims (2)

1. A device for dividing binary numbers, containing n parallel (n + 1) -bit adders (p-divisor divider) and n n-bit modulo-two adders, with output of the 1st digit of the sum (,. .., p + 1) j-ro parallel adder (, .. a, p) is connected respectively to the first input () -ro of the bit (j + 1) -ro of the parallel adder, the second input of the 1st bit j- ro of the parallel adder is connected respectively to the output of the (1-1) -th bit of the j-ro modulo two adder, the first input (il) -ro 0 of the bit of the j-ro modulo two adder is connected respectively to the input (i- 1) -ro bit and the device divider, the j-th bit of the dividend of which is connected respectively to the first input of the j-ro bit of the first parallel adder, (n + j) -and the bit of the divisible device is connected respectively to the transfer input of the (p – H) -th bit j-ro parallel adder, distinguished5 five Now, in order to extend the functionality by dividing the numbers represented in the additional code, a group of n EXCLUSIVE OR elements is entered into it, two elements are NOT and a private digitizer, and the divider input of the device is connected to the first input of the j-ro element EXCLUSIVE OR of the group and the first control input of the block of formation of private numbers, the second control input of which is connected to the output of the sign of the particular device, the input of the first element NOT and the output of the first element of the CLAIM A STUDY OR group whose second input is connected to the input of the Divisible Device Sign and the input of the third element, the output of which is connected to the second input of the first bit of the first. Parallel adder, the first input of the (n + 1) th bit of which is connected to the second j input -ro bit of the first adder modulo two and the output of the first element NOT; the output of the k-ro element EXCLUSIVE OR (k-2, 3, ..., n) is connected respectively to the second input of the first bit of the k-ro parallel adder,. the first bit transfer output of the j-ro parallel adder is connected to responsibly with the j-th information input of the block of formation of numbers of a private, j-th information output of which is connected respectively to the output of the j-ro bit of a private device, the m-th control output (, ..., p-1) of the block of formation of numbers of a private connected respectively to the second input (ha + 17th element EXCLUSIVE OR, second input of each j-ro bit (ha + 1) -th modulo two and the first input (n + 1) -th bit (t + 1 ) th parallel adder. 2. The device according to claim 1, characterized in that the block of formation of quotients of a private contains two groups of n adders modulo two and a group of n-1 elements AND, the first inputs of modulators two first groups connected to the first control input of the block The second input of the j-ro modulo two of the first group is connected respectively to the jM information input of the block, the rt-th control output of which is connected respectively to the output of the two modulo two of the first group, the output of the j-ro modulo two of the first groups connected according with the first input of the j-ro modulo two second groups, the output of which is connected respectively to the jth information output of the block, the second control input of which is connected to the second input of the nth modulo two of the second group, the first input element I of the group is connected respectively to the first input of the (n + 1) th modulo two second - groups, the second input of which is connected respectively to the second input of the m-th element of the group, the output of which is connected respectively to the second input of the m-th adder module two. dnd