SU1501278A1 - Reversible binary-decimal to binary code converter - Google Patents

Abstract

The invention relates to computing and can be used to build converters for large streams of binary and binary-decimal information. The aim of the invention is to enhance the functionality by providing conversion of integers and increasing speed. This goal is achieved due to the fact that the group of scaling converters 2 and the switch group 3 are additionally introduced into the reversible converter of the binary-decimal code into the binary one, containing the group of scaling adders 1 and 2, ill.

Description

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The invention relates to computing and can be used in general-purpose and specialized computers for constructing converters of large streams of binary and binary-decimal information.

The purpose of the invention is to expand the functionality by providing conversion of integers and increasing speed.

FIG. 1 is a block diagram of the proposed converter J in FIG. 2 - structural diagram of one of the options for implementing a scaling adder.

A binary-to-binary code to binary converter contains scaling adders 1 to 1 k-bit converters 2 to m + i switches 3 to 3, information inputs 4, to convertible groups of bits, input 5 of a binary decimal constant, input 6 binary constant, input 7 operating mode and output 8 of the converter.

Each scaling adder 1 contains multiplication nodes, adder 10, multiplicand input 11, multiplier input 12, control input 13, addendum 14 and logical zero input 15.

The basis of the converter is based on the following principle.

When converting a binary-decimal code to a binary source code, the n-bit code is divided into groups of k decimal digits in each. The conversion occurs according to the Gornar scheme, i.e. the first, the highest order itself, the bit group, is converted into a binary code and multiplied by a binary constant, the value of KOTopofi is determined by the value k. So, for example, with k 1 the binary constant is 1010, with k .2 the constant is 1100100, and so on. The resulting value is added with the binary value of the next, younger, group of decimal places. The result of the summation is again multiplied by the binary constant and summed with the binary value of the next, younger, group of decimal places, etc. until the binary value of the youngest group of decimal places is summed up. Conversion from binary to binary decimal occurs

similarly, but all actions are performed in the decimal number system. The value of the binary-decimal constant in this case also depends on the number of binary bits in the p groups. So, for example, when p 3 is a binary-decimal constant equal to 8, with p 6 constant

10 equals 64, etc.

In each of the scaling adders, operations can be performed on the numbers in binary and binary-decimal codes. When converting 5 SRI to binary code, they are tuned by the control potential from input 7 of the converter to information processing in binary code, and when converted to binary -0 code -0 for information processing in binary-ten code. On multiplication nodes, the product of some intermediate value is formed in the two-fold code;

The 25th number coming from the input 11 of the multiplicable adder 1, to the constant coming from its input 12 multiplier. The adder 10 collapses the two-row code of the obtained 30 product to the single-stage one.

In this case, through its free junior input 14, the value of the next, younger, group of bits of the number being converted is added and summarized.

35 free senior input - value О from input 15 of the converter. The control potential coming from the input 13 of the scaling adder ensures the operation of the multiplication node 40 and the adder 10 in the corresponding code.

The k-bit converters 2 - 2 ,, are designed to convert from a binary-decimal code to

45 binary and vice versa values of groups of bits coming from inputs 4 - 4,. With k 1 and p 3, there is no need for converters. The operation of the converters is done by the potential from input 7 of the device.

Switches 3 - 3 are designed to transmit to the inputs of the multiplier of adders 1, - 1 "values of either binary but-decimal (from input 5 of the device) or binary constants (from input 6 of the device). The operation of the switches is controlled by the potential from the input 7 of the converter.

Suppose that each scaling adder is designed in such a way that the multiplier in it is multiplied by two decimal digits or eight binary bits of a multiplier, and the number of scaling adders is three. Then the maximum number of convertible decimal bits is 8, and the maximum number of binary bits is 24.

We first consider the conversion from binary to decimal code. Let the number to be converted be 98356528. Before starting the operation, inputs 4, 4, 4 and 4 are set to binary-decimal values of 98, 35, 65 and 28, respectively. The control potential from input 7 of the device operation mode sets up the scaling adders 1, -1 for processing of binary codes, converters - for conversion to binary code, and switches 3 - 3h - for transmitting binary constants 1100100 from input 6 of binary converters of the converter. In scaling adder 1, the value 98 is converted into converter 2 into a binary code and multiplied by a binary constant. At the same time, the binary value of the number 35 generated at the output of converter 2 is added. From the output of scaling adder 1, the first intermediate result of the conversion is fed to the input of the multiplicable block C, 1 is multiplied by the binary constant, the binary value of the neighboring, younger, pair of decimal digits 65, formed at the output of converter 2, is added to the product. Second intermediate cut The slot in the scaling adder 1 is multiplied by a binary constant, the binary value of the number 28 obtained at the output of the converter 2 is added to the product, the final binary result is read from the output of the scaling adder 1.

When converting from binary to binary-decimal code at the input 7 of the converter, a control potential is set up which adjusts the scaling totalizers 1-1 for the processing of binary-decimal codes,

converters 2 - 2 - for converting from binary code to binary-decimal, switches 3 i - 3 j for transmitting binary-decimal constants 64 from input 5 of the device. Each of the inputs is supplied with six binary bits of the number being converted (input 4 is the oldest six bits, input 4. is neighboring, younger, six bits, etc.). After the triggering of the scaling summators 1 - 1 .J on output 8, the binary-decimal code of the transformed number is formed.

Claims (1)

Invention Formula 15 five A reverse binary-to-binary code converter, containing a group of scaling adders, the output of each scaled total adder of the output code of the group (Except the last one, is connected to the input of the multiplicand neighboring senior scaling adder of the group, the output of the last scaling adder 5 is the information output of the converter, the input of which operation mode is connected to the control inputs of all the scaling adders of the group, each scaling sum of the matrix consisting of the multiplier c of the adder, the first information input of which is connected to the output of the multiplier, the second information input of the adder and the multiplier input are respectively, the inputs of the addendum and the multiplier of the scaling adder of the group, the control input of which is connected to the control inputs of the adder and multiplier, which is and with the fact that, in order to extend the functionality by providing conversion of integers and speeding up, commutator groups and k-bit converter groups are introduced, the groups of scaling adders and switches contain m m 1 blocks where Q p is the number of bits of the output code, and k is the number of bits of the input code processed by one scaling adder, and the group of k-bit converters consists of () from the blocks, the information inputs of the first and second k-bit converters are connected respectively to information1 (the ionic inputs of the first and second groups of the converter, and the control inputs of all k-parallel converters and switches, are connected to the input mode of the converter, the output of the first The k-bit converter is connected to the input of the multiplicand of the first scaling adder of the group, the output i-ro (i 2,., tn + 1) of the k-bit converter is connected to the input of the term (il) -ro scaling adder, the input of the multiplier connected to the output of the (1-1) -th switch of the group, the first and second inputs of all switches of the group are connected respectively to the inputs of the Binary and Binary-decimal constants of the converter. W srig2