SU1095169A1 - Translator from binary-coded decimal code to binary code - Google Patents

Abstract

CONVERTER DVOICHNODESYATICHNOGO to binary containing a group of bit converters decimal digits into binary, and an adder, the outputs of which are outputs of the converter, whose inputs are connected to the inputs of bit converters, the outputs of the first discharge converter groups connected to the first input of the adder, the input of the first discharge Yes, the converter is the output of the first bit of the converter, characterized in that, in order to increase speed, a group of multipliers is introduced into it. NOT, and the bit converters of decimal digits into binary are made three-bit, and the outputs of all three-digit converters of the group, except the first, are connected respectively to the inputs of the multipliers, the outputs of which are connected to the inputs of the elements of the HE group, the outputs of which are connected to the second inputs of the adder, the outputs of the th three-bit converter of the group § (1 2-t j-yj), where m is the number of decimal digits of the converter, are connected (L to the first inputs of the adder with a shift of 10 (-1) bits to the side of the higher bits per first and second outputs of the first-stand trehrazr transducer groups are respectively outputs of the second and third bits of the converter, the logical unit whose input is connected to the input of the adder ate with the transfer. Oi f

Description

I1095169

The invention relates to digital technology and automation and can be used in the construction of converters in computing devices for data processing. A known converter of binary code to binary code, containing a group of adders and a circuit for setting binary equivalents of bits of a decimal code. Multiplying each digit-decimal code of digits by a factor of 10 is performed by decomposing factor 10 by numbers, multiples of powers of two, shifting the code of digits by a certain amount of bits to the left and then summing the shifted numbers T 3. The disadvantage of this converter is low speed which is related to the dependence of the conversion time on the number of digits in the decimal number. The closest in technical essence to the invention is a binary-decimal code to binary converter, containing a group of bit converters of decimal digits into binary and adder, the output of which are the outputs of the input converter; 9: which are connected to the inputs of the bit converters , the outputs of which are connected by t inputs of the adder C23. The disadvantage of this converter is relatively low speed, which is associated with an increase in the number of similar inputs of the adder with an increase in the size of the converter and, as a consequence, an increase in the number of accumulators of the adder. The aim of the invention is to increase speed. The goal is achieved by the fact that a binary-to-binary code converter containing a group of bit converters of decimal digits into a binary one and an adder whose outputs are the outputs of a converter whose inputs are connected to the inputs of the bit converters are outputs of the first digit converter of the group connected to the first inputs of the adder, the input of the first bit of the converter is the output of the first bit of the converter, the group of multipliers and the group of elements are NOT added, and bit converters of decimal digits to binary are made

all three-bit converters — the groups, except the first one, are connected respectively to the multiplier inputs, the outputs of which are connected to the inputs of the elements NOT groups whose outputs are connected to the second inputs of the adder, the outputs of the i-th three-digit converter of the group (), where m is the number of decimal digits of the converter, connected to the first inputs of the adder by a shift of 10 (i-1) bits towards the higher-order bits, the first and second outputs of the first three-bit converter of the group are respectively The outputs of the second and third bits of the converter, the input of the logical unit of which is connected to the transfer input of the adder. 1 shows the structural scheme of the proposed converter; in fig. 2 and 3 is an example of the implementation of a six-bit binary-decimal converter into a binary code. The proposed converter contains a group of three-bit converters 1.1-1.P, each of which converts three decimal digits into binary ones, a group of multipliers 2.1-2 (p-1), adder 3, inputs 4.1-4 K of the converter, outputs 5.1- 5N converter and a group of 6 elements NOT. The three-bit converters 1.1-1h can be used as the converter described in 3. The number of three-bit converters 1 is defined as the larger integer from dividing the number of inputs 4 by the number twelve. The number of multipliers 2 is one less than the number of three-bit converters 1. A six-decimal converter contains the first 1.1 and second 1.2 three-bit converters, a multiplier 2.1 consisting of four-bit adders 7-9, a group of elements NOT 6, an adder 3 consisting of from four-digit adders 10-14. The inputs of the first T.1 three-bit converter are connected to the inputs 4.1 ... 4.12. The inputs of the second 1.2 three-bit converter are connected to the inputs 4.13 ... 4.24, and the outputs M1 ... A / M O are connected to the inputs L 1. .A 10 and the inputs B 2 ... 611 four-slot dnghh adders 7 - 9. To the inputs of the PD, to the four-bit sum inputs L 11, A 12, B 12 mator 9 and four-bit adder 8 are fed 8 (Logical zero signal. The transfer output of the four-bit adder is connected to the transfer input P ,, four-digit adder 7, ne output The transfer of the four-bit adder 7 is connected to the transfer input Рр of the four-bit totalizer 8. Outputs of the S1 ... S12 four-sum The common adders 7-9 are connected to the inputs of the NOT elements of group 6. The outputs of the first 1.1 three-bit converter are connected to the inputs A1 ... A10 of four-digit adders 10 - 12 .. The outputs of the second 1.2 three-bit converter are connected to the inputs of All ... A20 four-bit totalizers 12–14. The outputs of the elements of group 6 are connected to inputs B4 ... 615 four-bit totalizers 10–13. At the inputs of the Rd, B, and Ba four-digit accumulator 10 and at the inputs of B 16.. 20 four-bit adders 13 and 14 a logical unit signal has been given. The transfer output of each of the four-bit totalizers 10–13 is connected to the transfer input P of the subsequent four-bit adder 11–14. Outputs S1. . . S20 four-bit adders 10 - 14 connectors with outputs 5.1 ... 5.20 converter. The proposed converter works as follows. The initial number is divided into groups of three digits each, three-digit converters 1.1-1p transform each group of digits into binary equivalents, then multiply the obtained binary equivalents of the groups by a factor of 10 and sum the resulting products p yes numbers from O to a number whose value is one less than the number of groups of three digits. After operation, the converters form binary equivalents, which are multiplied by factors of 10, 10, 10. The multiplication of the binary equivalent of a group by a factor of 10 °, 10, 10 is performed by subtracting from the binary equivalent of the group shifted by zero, ten, twenty bits right , the result of multiplying the corresponding binary equivalent of the number that translates the factor 1C, 10, 10. Let the number 326656763 be transformed. We write it as follows: 326656763 326-10-i-656-10 + 326 - 11048576-G32768N 4-763-X + 656 flQ24 + 64) 1 + 16384- (512 326- -, (16 + 8) + f2 + 2- (2 + 2) Ji +656;.) (2 + 23) + 7 63-2. The multipliers 2.1-2 (h-1) shift and sum those parts of the numbers that are subtracted from the respective terms. The subtraction operation is performed by the adder 3, for which the result of the first three-bit converter is transmitted to its inputs without a shift, the result of the second three-digit converter is transmitted to the inputs of the adder with a shift by ten bits, the result of the third three-bit converter is transmitted to the inputs of the adder with a shift of twenty bits, etc., the result of the first multiplier, related to the second three-bit converter, is inverted by a group of elements HE 6 and transmitted to the inputs of the adder 3 with a shift of three bits, the result of the second multiplier, referring to the third three-bit converter, is inverted by a group of elements of HE 6 and is transmitted to the inputs of the adder with a shift of six bits and so on. Let us now consider in more detail the work of a six-bit converter. At outputs C1 ... CU, a binary code of a number is formed that is equivalent to that supplied by inputs 4.1 ... 4.12. The upper three digits are provided at the inputs 4.13 ... 4.24. On the outputs of AM. . .M10 is the binary code of a number equivalent to the inputs 4.13 ... 4.24. At the outputs 5.1 ... 5.20 of the device, the binary code of the number is formed according to the formula 1024 + C-M 24-m (M 2 + + M2), where N is the binary code of the output number; M is a binary-decimal number code corresponding to the upper three digits; C is the binary-decimal code of a number corresponding to the lower three digits.

510951696

Tab. 1 and 2 contain codes of numbers, the drivers are two-samples of the outputs of the first 1.1 light summation schemes, the general

and the second 1.2 three-bit transform-number of the summation steps of the given

for four input numbers. The converter is four. General

Tab. 3 contains codes of numbers, the number of SIS microcircuits required at the outputs of the elements NOT 6. my to build a six-digit table. 4 contains codes of numbers, the generator, is equal to twenty, which are at the outputs 1 ... 20 four- Converter. С2Э for six

10 - 14.digital totalizers implies the presence of

Thus, the proposed pre-Yp tivod input adder. When,

The code generator allows for conversion when it can be executed in five

develop binary-decimal numbers of summed-up steps, we get binary ones, the number of digits of which is mo-game per degree total,

It can be, for example, from one to the neck, which allows for faster speeds. Bearing in mind that track images are prevailing.

Table 1

Table 2

Table3

TableD

Rig,

Fig.Z

Claims (1)

Binary- (Decimal to binary) CONVERTER containing a group of digit converters of decimal digits to binary and an adder, the outputs of which are the outputs of the converter, the inputs of which are connected to the inputs of the bit converters, the outputs of the first bit converter of the group are connected to the first inputs of the adder, the input of the first bit pre. the developer is the output of the first discharge of the converter, characterized in that, in order to improve performance, a group of multipliers and a group of elements are introduced into it it’s NOT, and the decimal to binary digit converters are three-digit, and the outputs of all three-digit converters of the group, except the first, are connected respectively to the inputs of the multipliers, the outputs of which are connected to the inputs of the elements of the NOT group, the outputs of which are connected to the second inputs of the adder, the outputs of the ίth three-digit group converter (ΐ = 2-ν, where tn is the number of decimal places of the converter, connected to the first inputs of the adder with a shift of 10 (1-1) bits towards the higher digits, the first and second the moves of the first three-digit group converter are respectively the outputs of the second and third bits of the converter, the input of the logical unit of which is connected to the transfer input of the adder.