SU752337A1 - Pseudodivision device - Google Patents

Description

The invention relates to digital computing and can be applied to the composition of the arithmetic devices of digital computers in the calculation of elementary functions. Devices are known that implement the pseudo-division operation when calculating elementary functions Y 1 / X, Y, Water X, Y LPG and containing registers, adders and shift nodes 1 and 2. The known devices have a limited speed with a time for implementing the pseudo-division operation proportional to n, where t is the delay is one-bit by the bottom of the torus and on an element of the AND-OR type. The closest to the technical essence of the present invention is a pseudo-division device containing the first and second registers, the first and second adders the first shift node, the outputs of the first register are connected to the first inputs of the first adder, the outputs of which are connected to the inputs of the first register, the outputs of the second gister connected to the second of the first adder, to the inputs of the first node shift and to the first inputs of the second adder, the outputs of the sums of which are connected to the inputs of the second register, the outputs of the first node shift n Connected to the second inputs of the second adder 2. The pseudo-division device performs the pseudo-division operation by implementing the recurrent IRIi, i 2 ratio (A -, Bj,., €, its4gnS ,; sign Ai, where,, 1 - X, HI X , 1 1.1, 2, 2, ..., nl, p-1; |., Ns Pl. The device operates cyclically. Each iteration is repeated twice, i.e., double steps are used to converge the computational process. However, the known device has a limited speed, since the number of executed iterations is proportional to n and it is necessary to perform operations on each executed iteration ation adding (subtracting) the proliferation carries by n bits. The purpose of the invention is to increase the speed of the pseudo-division device by eliminating hyphenations by n bits at each iteration being performed.

The goal is achieved by those in the pseudo-division device containing the first and second registers, the first and second adders, the first shift node, and the output of the first. the register is connected to the first input of the pair adder, the output of which is connected to the input of the first register P9, the output of the second register is connected to the second input of the first adder, to the input of the first offset node and to the first input of the second adder, the output of which is connected to the input of the second register, the output of the first shift node is connected to the second input of the second adder, the third and fourth registers are entered, the second shift node and the third adder, and the output of the third register is connected to the third input of the first adder, the output carries cat connected to the input of the third register; the output of the fourth register is connected to the fourth input of the first adder, to the input of the second shift node and to the third input of the second adder, the carry output of which is connected to the input of the fourth register; the output of the second shift node is connected to the fourth input of the second adder, the output of the sum of the high-order bits of the first adder is connected to the first input of the third adder, and the output of the high-order bits of the first adder is connected to the second input of the third adder.

The drawing shows a block diagram of a pseudo-division device.

The device contains the first register 1, the second register 2, the first accumulator 3, the second adder 4, the first node 5 shift, the third register 6, the fourth register 7, the second node 8 shift / the third adder 9 (with parallel transfer).

(The device performs a pseudo-sharing operation by implementing a recurrent relationship

.i 2 (A, .Bi),

(2)

B-iM B lg; 2 B.

 ° 1,

..,

where, l, 2, 2,,. . , o.-1, vs-1, oC, oC, o6, d + l, oi + 1, ..., 2 d. -1.2s -1.2s6, 2-6 660, 2 ° (: + 1., 2ot +1,..., Goiter - 1, Goiter - 1.3o., 3 (X, Zoe, 3ot + 1, 3od + l , ..., n - 2, n - 2, n - 1, nl, nl, dL (mi) / 2, Ai 1-X, BI X, - ef-1, t.lllc +1 m - the number of bits The third adder is less than the device's width n ,.

The device operates cyclically.

In this case, the first register 1. works simultaneously with the third register b, the second register is the 2nd fourth

The driver 7, the first node 5 shift about the second node 8 shift.

At the i-th iteration, the code of the digits of the magnitudes of A, from the outputs of the first register 1, enters the first moves of the first sumrator 3, the code of the transference of magnitude A | from the outputs of the third register 6 to the third inputs of the first adder 3. The bit code of the value Bj from the outputs of the second register 2 goes to the second

the inputs of the first adder 3, the inputs of the first node 5 shift and the first inputs of the second adder 4. The code transfers the value In, from the outputs of the fourth register 7 is fed to the fourth inputs of the first adder 3, to the inputs of the second node shift 8

and to the third inputs of the second adder 4. In the first shift node 5, the code of bit sums of Bj is shifted by 2j bits to the right, as a result, the code of bit bits of Bj is formed at the outputs of the first shift node 5, which is fed to the second inputs of the second adder 4. In the second shift node 8, a shift of the code of the transfer of quantity in occurs; on 2, . bit right. As a result, at the outputs of the second shift node 8 a transfer code of value 2 Bj is formed, which is fed to the fourth inputs of the second adder 4. In the first adder 3, depending on the value of j, the addition and subtraction of the value АJ and В) presented in the two-wire code , and at the outputs of the first adder 3, a quantity is formed (A j - & Bj), i.e. at the outputs of the sums of the first adder 3, a code of bit sums of the value (A j Bj) is formed, and at the outputs of the translations of the first adder 3 a code of the transfers of the magnitude (A - B) is formed. The code of bitwise amounts (Aj - Bj) from the outputs of the sums of the first adder 3 is shifted left by one bit to the inputs of the first register. 1, as a result, the code of bit sum values Aj, appears in the first register 1. 2 (A, B). The transfer code of the value (A j -; B, -) from the carry outputs of the first adder 3 is sent with a shift to the left ila two bits to

the inputs of the third register 6, as a result, in the third register b appears the code of transfers of the value Ai. 2 (A, - -) Bj). Thus, in the first register 1 and in the third register 6, the value (Aj) presented in the two-digit code appears. The highest bits of the code of the bit sums of the value () from the outputs of the sums of the highest m bits of the first adder 3 arrive at the first inputs of the third adder 9.

The older m bits of the carry code of magnitude (A - j B;) from the carry outputs of the older m bits of the first adder 3 arrive with a left shift by one bit to the second inputs of the third adder 9. In the third sum of the torus 9, the operation of the older m bits takes place The odds of the bit-sum code and the transfer code of the quantity (A i -; B;), i.e. at the outputs of the third adder 9, a binary code is formed of the most significant m bits of the value

SA B; ). From the output of the most significant (digit) bit of the third adder 9, the next digit of the pseudo-frequency one is taken off. At the same time, in the second adder 4, depending on the magnitude of the magnitude, the operation of adding or subtracting the B values, and presented in a two-row code, i.e. on the inputs of the second adder 4, a value is formed (B j +, 22 V;). Since the chains of sums and transfers of the second adder 4 are separated, the value (Bj B,) is formed on the ЕЫХОcs of the second adder 4 in the two-row code, i.e. The sum of the values of (Bj + B) is formed at the sum outputs of the second adder 4, and the transfer code of the magnitude (B; B,) is outputted at the carry outputs of the second adder 4. The code of bitwise amounts (Bj 2 V) is fed to the inputs of the second register 2, as a result, in the second register 2, the code of bit sums of the value Bj, B, B (, the code of the transfers of the value (B | +, 2Bj) comes with a shift to the left for one bit to the inputs of the fourth register 7, as a result, in the fourth register 7 it turns out the code of carries-be-2, B, 2

Faces-In

AT,. So

 one

Thus, in the second register 2 and in the fourth register 7, the value of BV m Bi appears, represented in a two-channel code. Since the determination is made only on the basis of m most significant bits of the AU value, the TH on the i-th iteration can occur an error of the magnitude A V, which distorts the pseudo-frequency one. The value of this error is less than 2. At the (I-1) -th iteration, the value of this error is doubled, i.e. less than 2 ..- In addition, at the (1 + 1) -th iteration an error may occur, the value of which is less than 2. Therefore, the total error at the i-th iteration and {1 + 1) -th iteration is less than 2.2 + 2. After the execution m iterations will be erroneous to all older m bits. Since each iteration is repeated twice, to compensate for this error o; -a, 2a; -a, zoe-a, ... iterations are repeated an additional time, where about (t - 1) / 2.

In this case, the distortion of the m higher bits is compensated.

After i (2n + 2n / (m - 1)) - a multiple of repeating iterations from the output of the most significant (digit) bit of the third adder, all digits of the pseudo-frequency will be removed; .

The effectiveness of the invention is to increase the speed of the proposed device by 5 times / compared with the known device — by eliminating hyphenation by n bits at each iteration when performing addition and subtraction operations, although the number of iterations is increased.

Claims (2)

1.Baykov V.D., Smolov V.B. Hardware implementation of elementary functions in digital computers. L. 1975, p. 3-23, with. 67-76. 2.Meggit J.E. Pseudodivision, and pseudomultiplication processes. IBM lournae Res.:8 DeveEop, 1962, y.6, 2, p. 210-226 (prototype).