SU1374217A1 - Device for multiplying n-digit numbers - Google Patents

Abstract

The invention relates to computing and can be used in the development of high-speed devices of multiplying asynchronous / A - j f-i f-g 4r4 iVl 5 lYl / l / l type. The aim of the invention is to enhance the functionality by multiplying negative numbers. This goal is achieved by the fact that a device for multiplying n-bit numbers containing accumulator I 3, group 4 of switches 5, matrix 6 elements AND 7, group 8 elements OR 9, group 10 decoders 11, group 12 elements OR 13, group 18 elements And 19, a group of 20 elements And 21, a group of 22 elements And 23, elements OR 24, 25 and a buffer register 26, additionally contains groups 14 and 16 elements OR and a combination adder 27. 2 Il. , L l

Description

113

 This invention relates to; to computing and can be used in the development of high-speed devices 1TU1 asynchronous type.

The aim of the invention is to expand the functionality by multiplying negative numbers.

Fig. 1 shows a diagram of the device for multiplying n-bit numbers for the case of Fig. 2, a functional diagram of the decoder.

The device (Fig. 1) contains the input 1 of the expandable device, the input 2 of the device multipliers, (2n-1) -discharge accumulating adder 3, group 4 of n switches 5, matrix 6 of

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-g- elements And 7, containing n / 2

rows and 2n-1 columns, first group 8 of 2n-3 elements OR 9, group 10 of n / 2 decoders 11, second group 12 of n / 2 elements OR 13, third group 14 of n / 2 elements OR 15, fourth group 16 of n / 2 elements OR 17, first group 18 of n / 2 elements I 19, second group 20 of n / 2 ale: ntov And 21, third group 22 of n / 2 elements And 23, first and the second elements SHS 24 and 25 (p / 2) -discharge buffer register 26, combinational adder 27, device logical zero input 28, device logical unit input 29, device clock input 30, and multiplex termination output 31 Properties.

The decoder 11 (figure 2) contains .element EXCLUSIVE OR 32 and elements AND 33-36.

The buffer register 26 is built on two-stroke triggers.

If signal 1 is present at the inversion output of the adder 3, then its input information is inverted, and signal 1 is generated as the input transferor 3.

The switches S of group 4 are designed to provide single or double multiplicative values to the inputs of the first group of matrix 6. If signal 1 is formed at the forward output of the first element OR 24, then the output of the switches 5 of group 4 transmits the value of a single multiplicand, otherwise, the outputs of the switches 5 of group 4 receive the value of a double multiplicand.

With the help of group 11 decoders, a 10-bit multiplier code with digits {o, 1 is converted into a code with T, O, 11. Below is a truth table explaining the operation of decoders 11 of group 10.

The device works as follows.

Let the multiplier be 10011, the multiplier is 0.011111, then the product of Y is 0.0100011101.

At its inputs 1 and 2 of the device, the multiplier and multiplier are represented by additional codes in the form of 1,0110 and 0,01111, respectively, and in the accumulating adder 3, the result 1,1011100011 should be formed.

Suppose that in the initial state of the device at its inputs 1 and 2 additional multiplicative and multiplier codes are received, and accumulating adder 3 and buffer register 26 are zeroed (the chains of setting accumulator 3 and buffer register 26 to zero (not shown). Then, at the second output ne The first decoder 11, and the first output of the third decoder 11 of group 10, signals 1 are generated (the upper output of the decoder 11 is the first, and the lower output is the fourth), which means the first (best) pair of multiples of the multiplier is converted to view 1, the second is to mind and third (oldest - to mean 1 by decoders 11, 10 -11z group is converted to the form factor 0.10001 Formed at the outputs of decoders, group 10 signals are maintained constant throughout the entire process of multiplying the numbers of data in the device..

According to the value of the signals generated at the outputs of the decoders 11, -11 of group 10, the inverse outputs of the elements OR 13, -13j of the second group 12 form the binary code a. 010, which serves as the first term for the combinational adder 2 (this addendum of adder 27 does not change during the whole process of multiplying the given numbers in the device; a, the lower order bit of the addendum; and its highest order bit). As the second term, of the combinational adder 27, the contents of the buffer register 26 are used. The value of this term changes during the multiplication process (at the beginning it is 313

neither, but at the end of multiplication it should be equal, i.e. for the considered example, at the end of the multiplication, the second term should be 101). The input carry of the combinational adder 27 continuously serves as a signal 1, which is fed through the input 29 of the device.

In the first step of multiplying at the outputs of the sum of the combinational spzmmator 27, a result is formed, 010 + 000 + 001 011. At the same time, only at the output of the first element And 23, the third group 22, the signal 1 is formed; first, through the first element And 19, the first group 18 and the first element OR 24 adjusts the switches 5 of group 4 to transmit a single multiplicand, secondly, it allows the transmission of this single multiplicand to the accumulating adder 3 from the outputs of the And 7 elements of the first row of the matrix 6 Thirdly, it adjusts the accumulator adder 3 through the first element 21 and the second group 20 and the second element OR 25 to invert its input information and generates a single signal of the input transfer of the adder 3, fourthly, prepares the input of the first (the youngest o) the discharge of the buffer register 26 and the entry into it 1.- With the arrival of the first clock pulse at the device input 30, it is allowed to receive the accumulating adder 3 from its bit inputs of the inverse value of information, as well as recording the unit to the first bit of the buffer register 26. This concludes the first cycle of operation of the device.

In the second cycle, simultaneously with the execution of the suppression in the accumulating-accumulating adder 3 and the formation in it of an intermediate result equal to 0.0000010011, the following actions are performed. At the outputs of the sum of the combinational adder 27, the value 010 + 001 + 001 100 is formed, as a result of which the output of the third element And 23, the third group 22

Signal 1 is generated. This signal performs the following actions: first, through the third element AND 19, the first group 18 and the first element OR 24 configures the switches 5 of group 4 to transmit a single multiplicand, secondly, it allows the transmission of this single multiplicand to the accumulating adder 3 from the outputs of the elements And 7

four

Q 5 0 5 Q. "

. j

five

0

five

the third row of the matrix 6, thirdly, prepares the input of the third (oldest) buffer register 26 to write to it 1. It should be noted that the input of the inverting accumulating adder 3 in this step does not generate a signal 1, since the output the third element OR 17z of the fourth group 16, a signal O is formed. With the arrival of the second clock pulse at the device input 30, reception into the accumulating adder 3 from its bit inputs of information without inverting is allowed, as well as writing the unit to the third (highest) bit of the buffer register 26. At the second cycle of the device is terminated.

Then, simultaneously with the summation in accumulating adder 3 and forming in it the final result equal to 0.0000010011 + 1.1011010000 1.1011100011, in the combinational adder 27 the codes 010 + 101 + 001 are summed up, as a result of which the output of its transfer forms a signal 1, which is fed to the output 31 of the device, signaling the end of the multiply operation.

The preloaded device allows

ABOUT

multiply two n-bit numbers on average per 3p / 8 cycles.

Claims (1)

Invention Formula A device for multiplying p-bit numbers containing a p / 2 bit buffer register, H2P-1) -discharge accumulator, matrix of n2 + n „- -2 elements And, containing n / 2 rows and n + 1 columns, the first group of 2n-3 elements OR, the second group of n / 2 elements OR, the group of n / 2 decoders, the first group of n / 2. elements AND, the second group of p / 2 elements AND, the first and second elements OR, a group of n switches and. the third group of p / 2 elements I, and the inputs of the multiplicable device bits are connected directly and shifted by one bit towards the older ones, respectively, with the first and second information inputs of the group switches, the outputs of which are connected respectively with the first inputs of the elec And the columns of the matrix, the first inputs of the elements of the And (n + 1) -th column of the matrix are combined and connected to the inputs of the highest bit of the multiplicand device, the inputs of the K-th element OR of the first group. (, 2,.,., p-3 ) connected to the outputs of k + 2-2 (1-1) -X elements AND ix rows of the matrix (, 2, ..., p / 2), the outputs of the elements OR of the first group are connected respectively to the inputs of bits from the third to (2n -1) -th accumulating adder, outputs of the first and second elements And the first row of the matrix are connected respectively to the inputs of the first and second bits of the accumulating adder, inputs the upper and lower bits of each pair of bits of the device multiplier are connected respectively to the first and second inputs of the corresponding decoder, the outputs of the AND elements of the first group are connected respectively to the inputs of the first OR element, the direct output of which is connected to the first control inputs of the group switches , the outputs of elements AND of the second group are connected respectively to the inputs of the second element OR, the first inputs of the elements AND of the first and second groups are connected to the second inputs of the elements AND, respectively- Bettyuyushu; s and the inputs of the corresponding bits of the buffer register, the recording resolution of which is connected to the clock input of the accumulating adder and to the clock input of the device, that is, in order to extend the functionality by multiplying negative numbers, it contains the third group of n / 2 elements OR, the fourth group of n / 2 elements OR and n / 2-razdny combination combiner, i-) the row of the matrix of elements And further contains n-2i elements AND, and the third input of the j-ro group decoder (, 3, ..., p / 2) com inn with the first input (j-i) -ro of the rpynnbf decoder, the third input of the first group decoder is the input of the logical zero of the device, the first outputs of the group decoders are connected to the pbr 0 5 0 five 0 five 0 the primary inputs of the corresponding OR elements of the second and third groups, the second outputs of the group decoders are connected to the second inputs of the corresponding elements OR of the second and third groups and the first inputs of the corresponding OR elements of the fourth group, the third outputs of the group decoders are connected to the third inputs of the corresponding elements of the second group, the fourth outputs group decoders are connected to the fourth inputs of the corresponding OR elements of the second group AND the second inputs of the corresponding OR elements of the fourth ruppe, the outputs of the elements OR of the third group are connected to the second inputs of the corresponding elements AND of the first group, the outputs of the IL elements of the fourth group are connected to the second inputs of the corresponding elements AND of the second group, the inverse outputs of the elements OR of the second group are connected to the inputs of the corresponding bits of the first summand combinational adder, the outputs the bits of the sum of which are connected to the first inputs of the corresponding elements AND of the third group, the second inputs of which are connected to the direct outputs of the corresponding elements ents OR of the second group, the first entrances. elements and columns of the (n + 2) -th (2n-1) -th matrix are connected to the input of the higher bit of the multiplicand device, the outputs of the elements of the third group are connected to the second inputs of the elements and the corresponding 1x rows of the matrix, the transfer input of the combinational adder connected to the input of the logical unit of the device, the transfer output of the combinational adder is the output of the end of multiplying the device, the inverse output of the first OR element is connected to the second; the control inputs of the group switches, the output of the second OR element is connected to the inverting input of the accumulating adder, the outputs of the buffer register bits are connected to the inputs of the corresponding bits of the second term of the combinational adder.