SU151117A1 - Dedicated adder - Google Patents

Description

In conventional devices, accelerated decimal multiplication, which uses summation of either multiplicand or double multiplicand, the cycle of operation is four clocks.

In the described decimal adder, as well as in the known device of multiplying the numbers represented in binary code with. "3, in order to increase speed for simultaneous wavosni and addition, example) s binary adders, included in the decimal adder interconnected through logic circuits and a decoder. (The cycle of his work instead of four three bars).

The drawing shows a diagram of a decimal adder in a device for multiplying numbers represented in binary code with an excess of "3.

The circuit consists of a conventional decimal adder / and a doubling control unit 2 (circled in dashed lines).

The numbers N vi М are sent to the circuit, and when doubling, the signal D is the synchronizing pulses S, Sa, 5, 58 coinciding with the fourth, third, second and first binary signs in the dzon-tetchrock, respectively, the output of the circuit is .V + 2.VI in the presence of a signal D to N} - M when there is no P1 (the availability of its inversion is D).

When submitting two numbers represented in the specified code, the correct transfer occurs for the E1 binary adder both between binary units in one decade and between decades. This requires correction:

a) if there is a transfer to the high decade, add three to the binary sum;

b) in the absence of a carry-., calculate three of the binary sum.

The correction can be performed by the additional binary adder 22, if subtraction "3 is replaced by adding" 13 and prohibiting (the C X 10 matching scheme) the transfer between the decades (this is true, since 2 - 3 16 - 3 13).

Doubling a binary number is equivalent to shifting by one bit to the left or delaying it by one clock cycle (with a delay line of Rg8) when fed to an adder. But since the scheme operates with binary-decimal numbers, it is necessary after doubled to carry out the same correction as after addition. The presence of a “transfer between decades in binary code with an excess of three when doubling is indicated by the presence of a unit in the sign“ 8 decades.

Thus, after doubling and adding, it is possible to carry out a general correction of the binary sum by the adder 22. But since the first (main) binary adder S1 doubles the number and -., Corrected, the transfer between the decades can be incorrect:

a) if there was a doubled h, then, before the correction, doubled the number will be with the lack of three and with binary sums 1111, 1110 and 1101, the adder / will not produce the transfer to the high decade, although it is necessary. These double digits are recognized by the acquisition scheme Cx8 and the matching scheme. If these numbers are present, the signal B is sent to the LH decoder, and the decoder at the same time generates an additional transfer signal Y, which through the CX collecting circuit 13 is fed to the input of the 3rd module of 21matmat 21;

b) if there was no “doubling transfer”, then before the correction the doubled number will be with an excess of three. The appearance of binary sums 0000, 0001 «0010 indicates that the adder 21 has developed a false transfer to the high decade. These sums are recognized by the schemes Cx and In this case, the decoder generates signals X, the inversion of which allows the transfer.

All the various options for doubling are tabulated. To illustrate the operation of the circuits, let's follow one example - row 5 of the table.

In the presence of a signal D, the number M through the coincidence circuit Cx5 is delayed by the line Ls8 "and one clock through the collection circuit CX is fed to input 2 of the adder 21.

Suppose it was the number 7 (1010), after a delay it was like 1 (0100), since 2 X, and if you throw away the tens, you get 4, therefore, the adder 22 should correct the sum, added 3 (OOP). I 1 I Supplement f, that the input / adder S1 at the same time was given the number 8 (1011). The adder gives the bottom amount of 0100 + 1011 + 1111. This sum is recognized by the scheme CX and Cx. A generation of B is generated indicating that transfer to the high decade is necessary. The decoder generates an additional transfer, which through the collection circuit CX enters the input of the adder 21 as a normal transfer. With transfer cash in addition, the binary amount must be on the correspondent by adding “3 (0011). Since the transfer of the ud was also required to add 3 (OOP), so it turned out that it was necessary to add 6 (0110). Decoder LH generates signals - | - CD + CDIz + + CE and K. BE + CE + CD. These signals through the delay line to the input 2 of the adder 22 are received as the code of the “ONO correction. Summing up with the binary sum of 1111, it gives the corrected value; the sum is IT + 1111. (1) 0101. Since the transfer to the senior decade is not skipped by the CUJ coincidence circuit, we get the rules {the sum of 2 (0101) - the least significant bit 7 X 2 + 8 22. It should be noted that the LH decoder generates signals only at the time SB, therefore, no strobing of the input signals is required. The decimal adder in the multiplication device of numbers represented in binary code with an excess of "3" with the implementation of the multiplier or double multiplicative method, characterized in that, in order to increase the speed, the same dioplate adders used for increasing the speed are doubled and added. in the des -.chny adder, connected between the logical circuit and the decoder. - 3 -Л 151117 The item is invented and