SU723571A1  Decimal number multiplying arrangement  Google Patents
Decimal number multiplying arrangement Download PDFInfo
 Publication number
 SU723571A1 SU723571A1 SU752144635A SU2144635A SU723571A1 SU 723571 A1 SU723571 A1 SU 723571A1 SU 752144635 A SU752144635 A SU 752144635A SU 2144635 A SU2144635 A SU 2144635A SU 723571 A1 SU723571 A1 SU 723571A1
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 SU
 USSR  Soviet Union
 Prior art keywords
 register
 adder
 transfer
 multiplier
 inputs
 Prior art date
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 241001442055 Vipera berus Species 0.000 claims description 23
 230000000875 corresponding Effects 0.000 claims description 13
 230000005540 biological transmission Effects 0.000 claims 1
 239000000470 constituent Substances 0.000 claims 1
 238000010586 diagram Methods 0.000 claims 1
Description
one
The invention relates to computing and is intended for use in decimal and universal arithmetical devices.
A device for multiplying decimal numbers is known, comprising multiplicative and multiplier registers, an adder and a control unit 1.
A disadvantage of the known device is its low speed.
Closest to the present invention is a device comprising a control unit, a multiplicable register, a multiplier register, an adder and a transfer register, the discharge outputs of which are connected to the first discharge inputs of the adder, the control unit input is connected to the output of the multiplier register, the control unit of which is connected to the first output of the control unit, to the first control input of the adder and to the first control input of the transfer register, the second control input of which is connected to the second output of the control unit, the third, The first, fifth, and sixth outputs of which are connected respectively to the second, third, fourth, and fifth control inputs of the adder, the transfer outputs of each bit of which are connected to the corresponding inputs of the transfer register 2.
A disadvantage of the known device is a large time spent on adding decimal numbers.
The purpose of the invention is to increase the speed of the device.
Claims (2)
 This goal is achieved by introducing into the device a recording block and a corrected multiplicative register, the bit outputs of which are connected to the first inputs of the corresponding bits of the transfer block, the second bit inputs of which are connected to the outputs of the corresponding bits of the register of the multiplicable, and the third inputs of the bits of the block the inputs are connected to the outputs of the corresponding bits of the transfer register, the second bit inputs of the adder are connected to the outputs of the corresponding bits of the recording unit, the control input of which is connected to a sixth output of the control unit and to the input of the multiplier register The discharge skorrekgirovannogo multiplicand register inputs connected to the outputs of the adder rows sootvegsgvuyuschih discharge. The drawing shows a diagram of the proposed device. The circuit includes an adder 1, a multiplier register 2, a multiplier register 3, transfer register 4, a control block 5, a recording block 6, and a corrected multiplicative register 7. The device works as follows. In the initial state, the multiplier numbers were fixed in the tetrads of the adder and register 2. In multiplier register 3, the multiplier code is entered, register 7 is fixed to zero, register bits 4 are set to one. The multiplication operation is performed in n cycles of two auxiliary clock cycles. First, the first auxiliary clock is executed. On the Start signal, the control unit 5 is expressed. The output signal at its output, which provides an increase in the content of all the tetrads of the adder by 6. Then, the register is entered in register 7 of the contents of the adder and the latter is reset. This completes the first auxiliary beat. Next, n cycles are performed, and the current number of the multiplier is worked out on each one, starting with the youngest. For the first cycle, the number of the multiplier is fulfilled. The control unit 5, when there is no signal at the input, generates a signal that starts the first addition cycle: the unit is subtracted from the code of the lower tetrad, the multiplier register 3, transfer to the tetrads of the adder 1 is allowed to add the codes of the tetrads of register 2 or 7. this, esl ;; during the previous summation in tetra de adder 1, a transfer occurs in the corresponding transfer register register setting 1, which ensures that an adder is transferred to this tetrad to sum the code of the corresponding tetrad register 7. If there is no transfer in the previous addition in this tetrad then the corresponding bit of register 4 of the transfer remains in the zero state, which ensures the opening of the corresponding bit of block 6 of the entry, which in turn ensures the transmission to this tetrad of code from the corresponding related register tetrade
 2. Upon completion of the transfer in adder 1, the transfer register 4 is reset. The addition cycle is considered complete after the binary summation of the contents of the adder with the code transmitted to it via block 6. In this case, in the bits of the register 4 transfer, corresponding to the tefad, in which the transfer occurred, a single value is set. 14 If there is no signal at the input of the control unit 5, the next addition cycle begins to be extracted. These clock cycles are executed until after the next clock cycle in the lower tetrad of register 2 the zero value does not appear. In this case, the control unit 5 generates a signal that provides a shift to four bits to the right of the codes in the register 3 and the adder 1 and one bit of the code of the transfer register 4, which ends the cycle of the lowerorder digit multiplier. All other cycles are performed in a similar manner. After the last one, the device performs the second auxiliary clock, which provides for the correction of the product recorded in the adder. At this cycle, the control unit's signal allows the subtraction of 6 of those tetrads in which no transfer occurred during the last addition. Thus, the introduction of the register of the adjusted multiplier and the block of the entry in the proposed device allows to reduce the time of addition of the codes in the adder, thereby increasing the speed of the multiplication operation. An apparatus for multiplying decimal numbers comprising a control unit, a multiplicative register, a multiplier register, an adder and a transfer register, the bit outputs of which are connected to the first bit inputs of the adder, the input of the control unit is connected to the output of the multiplier register, the control inputs of which are connected to the first output of the control unit, to the first control input of the adder and to the first control input of the transfer register, the second control input of which is connected to the second output of the control unit, t The fourth, fifth and sixth outputs of which are connected respectively to the second, third, fourth and fifth control inputs of the adder, the transfer outputs of each bit of which are connected to correspond to the inputs of the transfer register, in order to increase speed, the device is entered into a block of entry and a register of corrected multiplier, the bit outputs of which are connected to the first inputs of the corresponding bits of the block of entry, the second bit inputs of which are connected to the outputs of the corresponding constituent bits of the multiplicand register and the third inputs bits Named unit connected to the outputs of the respective bits of transfer register, the second bit; shye inputs
Priority Applications (1)
Application Number  Priority Date  Filing Date  Title 

SU752144635A SU723571A1 (en)  19750613  19750613  Decimal number multiplying arrangement 
Applications Claiming Priority (1)
Application Number  Priority Date  Filing Date  Title 

SU752144635A SU723571A1 (en)  19750613  19750613  Decimal number multiplying arrangement 
Publications (1)
Publication Number  Publication Date 

SU723571A1 true SU723571A1 (en)  19800325 
Family
ID=20622830
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

SU752144635A SU723571A1 (en)  19750613  19750613  Decimal number multiplying arrangement 
Country Status (1)
Country  Link 

SU (1)  SU723571A1 (en) 

1975
 19750613 SU SU752144635A patent/SU723571A1/en active
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