SU429423A1 - ARITHMETIC DEVICE - Google Patents

Description

one

The invention relates to computing and can be used in arithmetic devices of universal and specialized computers of parallel and sequential actions.

Computer arithmetic units are known that contain a term register and a result register, an adder, a bit-grid overflow analysis device, and a control device. These devices can detect the overflow of the bit grid and form the correct result of arithmetic operations during overflow due to the use of two sign bits in the adder circuit and the result register.

The disadvantage of such arithmetic devices is the presence of redundant equipment associated with the use of additional sign bit in the adder and result register circuits, and for sequential machines, in addition, an increase in the execution time of arithmetic operations.

The purpose of the invention is to increase speed and reduce equipment.

For this, in the proposed arithmetic unit, the first output of the overflow grid analysis circuit is connected to the first inputs of the two coincidence circuits.

the second inputs of which are connected via a second delay line with the shift output of the control unit, the third inputs with the output resolution of the first shift of the control unit, the fourth inputs of the first and second coincidence circuits are connected respectively to the zero and single outputs of the sign bit of the result register, the inputs of the sign bit of which The switches are connected respectively to the second and third outputs of the discharge grid overflow analysis circuit, the fourth input of the result register through the serially connected OR circuit "NOT connected to second and third outputs of the analysis circuit overflow discharge grid, outputs a coincidence circuit connected to said fifth and sixth inputs of result register and connected in series through the second circuit" and a second OR circuit "NOT - a seventh input of the result register.

This makes it possible to have one sign bit in the result and term registers and to reduce the time it takes to perform operations on numbers represented by the additional code.

The drawing shows a diagram of the arithmetic unit.

The device contains registers of the result / and the term 2; one-bit adder 3;

delay line 4; Circuit 5 Analysis. Overflow of the bit network; control unit 6, triggers 7; joint schemes 8, 9 and 10; scheme "OR //; schemes “NOT 12; delay line 13; matching schemes 14 and 15; control unit outputs 16, 17; schemes ".OR 18 and 19; schemes "IE 20 and 21; control unit outputs 22-26; triggers 27-30, delay line 31.

The device works as follows. Before the start of an arithmetic operation (addition, subtraction, etc.), one of the operands is on the shift register / result, the other on the shift register 2 is a term. Both operands are fixed-numbered binary numbers, written in an extra code. To record the sign of numbers in registers 1 and 2, one trigger is used in each register. The operation of addition (subtraction) begins with the arrival of shifting pulses from output 16 to registers / and 2. With the arrival of the registers of the first shifting pulse to the inputs of the one-bit adder 3, the lower bits of both operands arrive. The result of the addition through the coincidence circuit 8 is written s trigger 27 sign register register 27 / according to the write enable signal at output 22 produced by control unit 6. With the receipt of the registers} and 2 second shift pulses, the next bits of operands arrive at the inputs of the adder 3 and add up to It takes into account the transfer signal from the delay line 4. At a time when the shift pulse arrives, the result from the addition of the previous, lower bits, recorded in the sign bit, is written to the trigger 28 of the higher type of mantissa of the result register. and the next result obtained on the accumulator from the addition of the higher bits of both operands is written to the sign bit of this register.

With the arrival of the registers / and 2 of the n-th shift pulse, the adder 3 receives the sign bits of both operands, and the sign bit of the result register 1 records the result of the addition of the sign bits of both operands taking into account the transfer from the delay line 4. Iri In this case, the sign of the result will always be true if the arithmetic unit’s discharge grid does not overflow. Otherwise, the value of the sign bit turns out to be incorrect and is corrected using the coincidence schemes 9 and 10, the overflow analysis circuit 5, the OR 19 circuit and the IE 21 circuit during the last ' THEREFORE, if in the sign bits of registers 1 and 2, units were recorded and there was no transfer from the output of the delay line (the first combination of overflow ip and y / s, where a „-" 1 sign bit of register I, bn - " 1 sign bit

register 2, c. .1 - “On transfer from the addition of older bits (.ma.ntissy), then the coincidence circuit 10 is triggered, forcibly sets the trigger 27 to the sign bit of register 1 to the single position corresponding to the true value of the sign bit . At the same time, the signal from the output of this circuit 10. is fed to the inputs of the OR 11, 19 circuits, sets the trigger 7 of the overflow analysis circuit to the single position, and using the IE 21 circuit, prohibits the operation of the result register circuit 8 / through which the addition result is written to the sign bit of this register.

The correction scheme also works in the same way if in the sign bits of both operands zeros were written, and the transfer from the addition of the higher bits of the mantissa is equal to one. (The second combination of overflow a b b with, where a b is “About the sign bit of the result register /, 6„ - “About the key bit of the register of the term 2, Ci, - -“ 1 p. Renos from the addition of the higher bits of the mantissa ).

In this case, the coincidence circuit 9 is triggered and forcibly sets the trigger of the sign bit of register 1 to the zero position, which corresponds to the true value of the result of the sign bit. At the same time, the signal from the output of the coincidence circuit goes to the OR / and 19 circuits, sets "1 on trigger 7 and disables the operation of the co-ownership schemes 8 of the result register.

Thus, the final result of the performed arithmetic operation with the true value of the sign bit will be formed on the result register / losle of the arrival of the n-shifted Imluses. At the same time, in the event of overflow of the discharge grid of the arithmetic unit, an overflow sign recorded on the trigger 7 will be generated | Miro.

When organizing arithmetic modified shifts of the result obtained (for example, in multiplied and real operations), it is necessary to take the first shift (check the result / take into account the value of the “missed additional significant digit, i.e. when organizing the first modified shift result 1, in case of overflow of the discharge grid of the arithmetic unit, it is necessary to set the most significant bit of the mantissa of this register to the position opposite to the position of the sign bit, which corresponds to one and; two overflow combinations 10 and 01, and then, when organizing the second and subsequent shifts, produce an ordinary shift. This problem is solved using the matching schemes 14 and 15, the scheme "OR 18, the scheme" NOT 20 together with the scheme 5.

If the output has 16 left shift pulses simultaneously with the signal times