SU547766A1 - Dividing device - Google Patents

Description

(54) DEVICE FOR FISSION

one

The invention relates to the field of computer technology and can be applied in digital instruments for processing measurement results.

Known devices for dividing, containing registers of operands, adder and logic elements p ..

The disadvantage of these devices is the low speed and redundancy of the equipment.

It is also known a device for dividing, containing the register of the dividend, the register of the divider, the buffer register, the key, the inputs of which are connected to the first outputs of the register of the divider and the buffer register, respectively, the output of the key is connected to the input of the counter and the counting input of the trigger which is connected to the output of the register divisible 2.

However, the device has an inoperative speed.

The aim of the invention is to increase speed.

This is achieved by imposing a pulse distributor, an element

OR and two groups of bit elements AND, connected in series with each other in each group, the outputs of the pulse distributor are connected to the corresponding one-bit inputs of the dividend register, the divider register AND of the buffer register, the control input of which is connected to the trigger output and the control input of the register the divider, the bit outputs of the register of the divider and the buffer register are connected to the inputs of the AND elements of the corresponding group, the outputs of the elements AND of each group of elements AND are connected to the inputs of the OR element, the output which is connected to the first input of the pulse distributor, the second input of which is connected to the control input of the device.

The drawing is a diagram of the proposed device.

It consists of a register of divisible 1, register divider 2, buffer register 3, key 4, trigger 5, counter 6, block 7 for fixing the end of division, pulse distributor 8, groups of elements 9 and 10 of element 11 or 11.

The operation of the device is as follows.

The counting pulses coming through the valve 8 are fed to the counting inputs of the first bits of the register of the divider 2, the buffer register 3 and the register delimog

1. The number of counting pulses received at the counting input of the first bit of the divisible counter 1 in one subtraction cycle is determined by the value of the first digit of the divisor. In addition, the counting pulses are subtracted

from the value of the divider stored in register 2, and summed in buffer register 3 When the number in the first digit of register 2 becomes equal to O, the first group of elements AND triggers, which through the element OR 11 controls the operation of the distributor 8. After the command signal is received, the distributor 8 produces counting pulses arriving at the counting inputs of the second bits of registers 1, 2 and 3. Thus, the circuit works as long as the valve begins to produce counting pulses arriving at the inputs n of the bits of the registers 1,

2 and 3, where the number of bits n is determined by the capacity of the register of the divider 2. The output signal of the key 4 is fed to the counter 6 and

to trigger 5. At this, trigger 5 switches and changes the counting direction in registers 2 and 3. When the number in register 3 becomes equal to O, key 4 is activated (the second subtraction cycle has ended, etc.). The end of the division operation is determined by the block by the moment of transition through About the number in the register of the dividend 1.

The use of additional elements - the distributor, the OR element and the groups of elements AND for every decimal bit distinguishes the proposed division device from the known device, since it has a much higher speed. To perform the division operation in this device, 10-L counting pulses are needed, where P is the number of decimal

bit divider. Compared to the prototype o, the speed will be in

time

iO-tt

more.

Claims (2)

1. Richard, RK. Arithmetic Operations on Digital VMs, M.-L., Foreign Literature, 1957, Ch. 9, p. 265-ЗО2. 2. USSR author's certificate No. 342187 M. Cl G06 f 7/52, 1972.