SU653746A1 - Binary pulse counter - Google Patents

Description

one

The invention relates to a pulse technique, namely counters of digital computing devices.

A binary pulse counter is known that contains triggers with input logic elements, the outputs of which are connected to the trigger inputs, a through transfer unit consisting of sequentially connected logic elements. The outputs of the logical elements of the NAND of the end-to-end transfer unit are connected to the inputs of the input logic elements of the counter bits. In the end-to-end transfer unit, the forward and inverse values of the transfer signal are generated at each digit of counter 1.

However, this binary counter does not provide the necessary speed and has a complex end-to-end transfer unit.

Also known is a binary pulse counter containing triggers with input logic elements 2И-OR-NOT, the outputs of which are connected to the inputs of the triggers, a through transfer unit consisting of consecutively connected logic elements 2И-OR-NOT and AND - NOT. The outputs of logic elements 2I-OR-NOT block

THROUGH MOVEMENT is connected to the inputs of the input logic elements 2I-OR- —NON the even bits of the counter. The counter also contains a logical NAND element, the input of which is connected to a zero signal source, and the outputs are connected to the inputs of triggers of even bits and the inputs of input logic elements 2И-OR-NOT odd bits. The corresponding outputs of the odd-bit triggers are connected to the inputs of the logical elements AND of the IS-block of the end-to-end transfer, and the outputs of the triggers of even bits are connected with the inputs of the logical elements of the II-OR-NOT of the block of the through-carry. In the end-to-end transfer unit, the forward or inverse value of the transfer signal is generated at each digit of counter 2.

However, the scheme of this binary pulse counter is complicated,

The purpose of the invention is to simplify the counter.

This is achieved by the fact that in the proposed binary pulse counter, which contains triggers with input logic elements 2И-OR-NOT, the outputs of which are connected to the inputs of the triggers, the end-to-end transfer unit, consisting of sequentially connected logical elements AND-NOT and input element AND-NOT , the outputs of the end-to-end transfer unit are pairwise connected to the first and second inputs of logic elements 2И-OR-NOT odd bits, the zero bus through the logical element AND-NOT connected to the first and third inputs of logical elements 2И-OR-NOT even and odd bits, respectively, the direct output of the trigger of each bit is connected to the fourth in odd and second to even input element 2 AND-OR-NOT of this bit, the inverse output of the trigger of odd bits connected to the fifth input of logic element 2I -OR-NOT of this bit, the corresponding inverse transfer signal in the next bit is connected to the third and fourth inputs of logic elements 2I-OR-NOT even bits, and to the fifth and sixth inputs - to the direct transfer signal bus previous bit d and forward output trigger previous discharge. In the end-to-end transfer unit, the forward and inverse values of the transfer signal are generated only into odd bits of the counter. In the end-to-end transfer unit, complex logical elements 2И-OR-NOT are replaced with simple logical elements AND-NOT, which simplifies the circuit of the counter.

The drawing shows a structural electrical circuit of a binary pulse counter.

The counter contains functionally complete triggers 1-4 (bits). They consist of an auxiliary and main trigger (not shown), which determines the following properties of all the bits of the counter: the signal applied to the input of the functional full trigger changes its state to the next clock time, after the end of the clock the trigger is automatically zeroed if there are no control signals at the input. The counter also includes a block 5 of end-to-end transfer consisting of consecutive AND-NES logic elements, input logic elements 6-9 2AND-OR-NOT and logic element 10 AND-NOT, to the input of which the zero signal is given. The input pulses are fed to the input of block 5. The output signals are taken from the direct outputs of the counter bits. The outputs of the counter bits have natural weights: 2 °, 2, 2, 2. They are connected to the corresponding inputs of the flip-flops 1-4. The outputs of the logical elements of the AND-NOT unit 5 are connected to the inputs of the logical elements of 6 8 odd bits 1, 3 counters. The inputs of logic elements 7, 9 even bits 2, 4 of the counter are connected to the bus of the inverse signal of transfer to the next (third) bit, the thickness of the direct transfer signal to the previous (first) bit and the direct output of the previous (first) bit trigger yes counter A source of zeroing signals through a logic element 10 is connected to the inputs of logic elements 6-9. The counter works as follows.

The impulse of the zero signal source is fed to the input of logic element 10, the signal from the output of which prohibits the regeneration of the contents of bits 1–4 of the counter. All counter bits are set to zero. The input pulses arriving at block 5 are summed in a binary counter. The first input pulse through element 6 records the unit on the trigger 1 of the first bit of the counter. On the remaining counter triggers regeneration occurs. The state of the counter will be 0001. The second pulse through element 7 records the unit on the trigger 2 of the second discharge of the counter and prohibits the regeneration of the trigger 1 of the first discharge of the counter. On the remaining trigger triggers

- regeneration occurs. The state of the counter is 0010. The third impulse through element 6 records the unit on the trigger 1 of the first digit of the counter. On the remaining counter triggers regeneration occurs. The state of the counter, - OOP. The fourth pulse through two consecutively connected logical elements of the IS-NOT of block 5 and element 8 records the unit on trigger 3 of the third counter and at the inputs of elements 6, 7 prohibits regeneration of the triggers 1, 2 of the first and second counter of the counter. On the remaining counter triggers regeneration occurs. The state of the counter is 0100. The fifth pulse through element 6 records the unit on the trigger 1 of the first digit of the counter. On the remaining counter triggers regeneration occurs. The state of the counter is 0101. When the next pulses arrive at the input of block 5, the binary counter works in the same way.

Claims (2)

1. Forward Germany No. 2217633, cl. 21 a 36/22, 1974. 2. For the number 2326734/21, cl. H 03 K 23/02, 1976, according to which, the decision to issue an author's certificate was made.