SU675421A1

SU675421A1 - Digital squarer

Info

Publication number: SU675421A1
Application number: SU762354469A
Authority: SU
Inventors: Вячеслав Иванович Ремнев
Original assignee: Remnev Vyacheslav
Priority date: 1976-04-26
Filing date: 1976-04-26
Publication date: 1979-07-25

Description

(54) ЦИФРОВОЙ КВАДРАТОР(54) DIGITAL SQUARE

I - I -

Изобретение относитс к вычислительной технике , а именно к арифметическим устройствам возведени числа в квадрат, и может быть использоваио в вычислительных маишнах, где операци возведени в квадрат вл етс специфической .The invention relates to computing, namely, to arithmetic devices for square-counting, and can be used in computing mainshells, where the square-cutting operation is specific.

Известно устройство дл возведени в квадрат Двоичных чисел, содержащее регистры, элементы И, делитель импульсов и генератор импульсов 1.A device for squaring Binary numbers, containing registers, AND elements, pulse divider and pulse generator 1, is known.

Недостатком этого устройства вл етс его сложность.A disadvantage of this device is its complexity.

Наиболее близким по технической сущности к предлагаемому вл етс цифровой квадратор, содержащий вычитающий счетчик, первую группу элементов И, вторую группу элементов И, сумматор , входы которого соединены с выходами элементов И первой группы, первые входь которых соединены с выходами вычитающего счетчика , входна шина квадратора соединена с входами вычитшощего счетчика и сумматора 2The closest in technical essence to the present invention is a digital quad, containing a subtractive counter, the first group of elements is And, the second group of elements is And, the adder, the inputs of which are connected to the outputs of elements And of the first group, the first input of which is connected to the outputs of the subtractive counter, quad input bus connected to the inputs of the subtractor and adder 2

Однако помимо сумматора и блока коррекции в .состав устройства вход т два регистра, значительно усложн юшие конструкцию. СложенHowever, in addition to the adder and the correction block, the device consists of two registers, a much more complicated design. Complicated

и блок коррекции. Количество вход щих в него элементов возрастает с увеличением разр д- ; ной сетки сумматора.and a correction block. The number of elements included in it increases with increasing bit size; Node grid adder.

Цель изобретени - упрощение квадратора.The purpose of the invention is to simplify the quad.

С этой целью в него введены первый и второй элементы задержки, элемент ИЛИ, причем выходы вычитающего счетчика соединены с первыми входами элементов И второй группы, вторые входы которых соединены с шииой опорной частоты, а выходы - с управл ющим входом выщ1тающего счетчика, первым входом элемента ИЛИ, через первый элемент задержки со вторым входом элемента ИЛИ, выход которого через второй элемент задержки соединен ро вторыми входами элементов И первой группы .To this end, the first and second delay elements, the OR element, are entered into it, and the outputs of the detracting counter are connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the reference frequency, and the outputs to the control input of the counting counter, the first input of the element OR, through the first delay element with the second input of the OR element, the output of which through the second delay element is connected by the second inputs of the AND elements of the first group.

Цредлагаемый цифровой квадратор работает по принципу вычислени квадрата числа с помощью арифметического р даThe proposed digital quad works on the principle of calculating the square of a number using an arithmetic series

12 fc1 1;12 fc1 1;

22 .1+24-1 4;22 .1 + 24-1 4;

И-2+3+2-И 9; I-2 + 3 + 2-I 9;

Claims

4 1 + 2 + 3 + 4 + 3 + 2 + 1 16. Then for the n-th term in general, the equation takes the form a p tn. The drawing shows a block diagram of the proposed device. . . The quadrator contains the subtractive counter 1, the first 2 and the second 3 group of elements AND, the MeitTbi delays 4 and 5, the elements OR 6, the adder 7. The input bus 8 into the device pulses the number to be squared at the input 9 and receives the reference frequency. Output (Each i-ro digit of the counter through the elements of the second group controls the passage of the reference frequency into the device and simultaneously through the corresponding group of elements I 3 is connected to the input of the i-ro digit of the adder. The device works as follows. When entering the number n on the input bus 8, it enters the adder 7 and the subtractive counter 1, through which it acts on the elements of the second group 3. The device receives the reference frequency.With the arrival of the first pulse, the number in the counter 1 becomes equal to (n-1). proh It is sent through the element OR 6, W; the second delay element 5 acts on the elements AND of the second group 2. The number (n-1) from counter 1 enters the adder 7. The pulse delayed by the first half of the period by the delay element 4 re-affects the elements AND of the first group 2. Thus, for one period of the reference frequency, the number from counter 1 will be entered twice into the adder 7. With the next pulses, the process repeats.When the contents of counter 1 go down to zero, elements AND of the second group 3 prohibit the passage of the reference frequency into the device. you and the process Numerical terminated. In the adder 7 - the number is equal to the square of the number received by the input slot 8. The use of the proposed device will reduce the amount of equipment used in comparison with the known devices. The invention of the Digital square (adrator containing a subtracting counter, the first group of elements is And, the second group of elements is And, the adder, the inputs of which are connected to the outputs of the elements And of the first group, the first inputs of which are connected to the outputs B1 of the reading counter, the input bus of the quadrator and an adder, differing by that., about the purpose of simplifying the quad, the first and second delay elements, the OR element, are entered into it, and the outputs of the subtractive counter are connected to the first inputs of the AND elements of the second groups, the second inputs of which are connected with the length of the reference frequency, and the outputs with the control input of the counter, the first input of the element ii, through the first delay element, with the second input of the OR element, whose output through the second delay element is connected to the second inputs of the elements And the first group. Sources of information taken into account during the examination 1. USSR author's certificate N 364934, class G 06 F 7/38, 1972. I

2. USSR author's certificate N 362298, cl. G 06 F 7/52, 1972.