SU924725A1 - Device for setting boundary conditions - Google Patents

Description

The invention relates to analog-c digital computing and is intended to set time-varying boundary conditions for solving heat conduction problems on hybrid and analog computers. Devices are known to simulate the boundary conditions in which the assignment of boundary conditions is performed using functional analog converters predstabl constituents are fairly complex devices tn. The closest in technical essence to the present invention is a device containing registers, digital-analogue converters, pulse generator, cycle counter, digital storage and resistor grid 21. This yctro is designed to set time-varying boundary conditions, and the storage (memory block ti-) the amplitude values of the functions are stored for each time step, i.e. the principle of piecewise-step approximation is realized, which makes the device more complex. In addition, the assignment of boundary conditions to the channels is carried out sequentially, which significantly increases the time to solve the problem. The purpose of the invention is to simplify the design of the device and increase its speed. To achieve this goal, a device for setting boundary conditions, containing a pulse generator, the output of which is connected to the input of a time step counter, an address register, the output of which is connected to the inputs of memory blocks, digital-analog converters, whose outputs are connected to the corresponding boundary nodes of the resistor grid, additionally the decoder and add blocks are entered, the output of the time step counter through the decoder is connected to the input of the address register, and the outputs of the memory blocks are respectively connected They are not connected to the inputs of the corresponding addition blocks, the outputs of which are connected to the inputs of the corresponding addition blocks, the outputs of which are connected to the inputs of the corresponding digital-to-analog converters.

Each addition block contains an adder, a sum register and a register of the addendum, the first input of the adder is the input of the block, and the output of the adder is connected to the input of the sum register, the output of which is the output of the block and through the register of the addendum to the second adder.

FIG. 1 is a diagram of the device; FIG. 2 is a piecewise linear approximation of a function.

The device contains a pulse generator 1, a resistor grid 2, a 3 time step counter, a decoder, an address register 5, memory blocks 6, addition blocks 7, each of which consists of an adder 8, a sum register 9, registers 10 of the addendum, digital-analog converters sources of stress) 11.

8, a device for specifying boundary conditions is used. Line-approximation approximation.

In order to simplify the description of the algorithm of operation of the device, we consider a specific case of a function approximated by three segments (figure 2). Considering that the instrument is time t

G -, (t) a ,, GQ, (,

PW (t) a ,,.

The coefficients a;, G (t and a (j (t; j) coincide with the values of the function F (t) at these points. As an approximated function F (t) there may be dependencies of the heat transfer coefficients d (t) - for boundary conditions type, medium temperature T (-fc) for boundary conditions I and | type and heat flux g (t) for boundary conditions IJ ood.

In order to parallel the boundary conditions to all boundary points, the indicated dependencies are approximated by the same number of segments for equal time intervals, which consist of an integer number of time steps At.

The increment functions for the i-th time interval are written to the memory blocks 6, and the values of the boundary conditions at, i.e. Ed.

The decoder t proceeds to the next time interval by converting the current time step number recorded in counter 3 | to the number of the time interval, which is the increment address bjut for the given interval.

The device works as follows.

Generator 1 is started. When the first pulse arrives at counter 3 in register 5 using decoder 4, an increment address is generated for the first time interval. This address is fed to the address inputs of memory blocks 6, with the result that the increment codes come from the outputs of memory blocks 6 to the first inputs of adders 8, which add them to the codes of the initial boundary conditions a received from the registers 10 of the addendum. At the output of the adders 8, the values of the functions for the first time step (e.g., Fig. 2, point A) are formed, which are stored in the sum registers 9. The boundary conditions information is fed from the outputs of the registers 9 to the inputs of the respective converters 11, where it is converted to analog form and fed to the boundary nodes of the grid 2, as well as to the registers 10, where it is memorized until the next time step.

Claims (2)

With the arrival of the second pulse, the formation of the boundary conditions for the second time step neipBoro time interval is formed. This will continue until the current time step number reaches the number characterizing the number of steps in the first time interval. For this case (figure 2), this number is A. 5 After reaching the specified number, with the arrival of the next pulse to counter 3, the decoder C generates the address of the second increment and blocks 6 of the memory output an increment to the adders 8, in which the formation of the boundary values conditions for the first step of the second time interval, etc. The formation of boundary conditions at the following time intervals occurs in a similar way. Thus, the implementation of the device in accordance with the invention makes it possible to significantly reduce both the time to solve the problem and the cost of setting boundary conditions when solving field theory problems. Claim 1. Device for setting boundary conditions, containing a pulse generator, the output of which is connected by the input of a time step counter, an address register, the output of which is connected to the inputs of memory blocks, digital-analog converters, the output of which is connected to the corresponding boundary nodes of the resistor grid, In order to simplify the device and increase its speed, a descrambler and addition blocks are additionally introduced into it, and the output of the time step counter is connected through the decoder input of the address register and the memory block outputs are respectively connected to the inputs of combining matching blocks whose outputs are connected to inputs of the respective digital-analog converters. 2. The device according to claim 1, of which is that each addition block contains an adder, a sum register and a term register, the first input of the adder being the input of the block, and the output of the adder is connected to the input of the sum register, the output of which is the output of the block and through the register of the addend is connected to the second input of the adder. Sources of information taken into account in the examination 1. The author's certificate of the USSR (f 239675, cl. G About G, 1967. 2. USSR author's certificate number 221957, cl. G 06 G, 1966 (prototype). P - b P . 6 P b sh fig /