SU603988A1 - Cubic root extracting arrangement - Google Patents

Description

-ILK 6, driver 7 pulses, accumulating adder 8, input 9, output 10, bus 1 of installation to one state.

The algorithm of the device is based on an iterative expression

 pz - (p-1) s 3p (p-1) + 1, (1) where n 1,2,3 ....

If we consider that the production of Zi is the sum of the (n-1) -ng members of the arithmetic

progression of the form Si ao + gi with ao 0 and g 1,

/ 7fr-jj -J t. e. d can be written. „J

pz - (p-1) 3 2; 3i + l (2) We will assume that n m, then the iterative expression () can be used to build a device that performs the calculation of n, where is a part of the number.

The device works as follows.

In the initial position, all bits of the counter 1 are set to one, and the bits of the counter 6 and accumulating adder 8 are set to the zero state. Triggeo 3 is also set to zero. The number, t, from which the third-degree root is extracted, is supplied in the number-pulse code to the input 9 of the device. When the first pulse of the input sequence arrives, the counter 1 overflows and the overflow pulse from the output of this counter goes to delay element 2 and the first input of the OR element 5. From the output of the OR 5 element, the overflow pulse arrives at the counting input of counter 6, thereby writing one into it. After time r, determined by the delay element 2, the pulse arrives at the counting input of the trigger 3, the first input of the element 4, and the input of the pulse shaper 7 from the voltage drop. With the falling edge of this pulse, the trigger 3 is set to one state and the pulse shaper 7 is started, and since before this the trigger was in the zero state, the pulse 4 does not pass through the pulse. The pulse shaper 7 generates a pulse with a duration t ".", Which is fed to the clocking input of the accumulating sum.mattor 8 and the clocking input of the counter 1 record. the accumulating adder, the inverse code of the accumulating adder is rewritten into counter 1 with a shift of one bit in the direction of the seniors, and one is recorded in the lower digit of the counter. Thus, in code 1, an additional code will be generated up to seven, and when the following pulses of the input code arrive at this counter, the next overflow signal at its output will be generated when a pulse arrives, the number of which in the input sequence is 1 + 7 8. From the counter output 1 pulse overflow enters the delay element 2, as well as through the element OR 5 - to the counter 6, thereby forming a code equal to two in the counter 6. The pulse from the output of the delay element 2 is fed to the counting input of the trigger 3, the input of the pulse shaping device 7, and also through the open element AND 4 and the element OR 5 to the counting input of counter 6, thereby forming a code equal to three in this counter. By the falling edge of the delayed pulse, the trigger 3 is set to the zero state, and the pulse shaper 7 is triggered. With the output pulse of this driver, a code of six is added to the contents of the accumulating adder, resulting in a nine-time form in the accumulating adder. By the same pulse, the inverse code of the accumulating adder is rewritten into counter 1 with a shift by one bit of the direction of the seniors,

and one is written to the younger digit of the counter. Thereby, in the counter 1, a code will be generated that is additional to nine-nineteen. When the following I pulses of the input code reach the counter I, the next overflow signal at its output will be formed when a pulse of the input sequence arrives, the number of which is 8 + 19 27.

Thus, in accordance with the structure of expression (2), counter 6, together with elements 2, 3, 4, 5, performs the calculation

member 31, accumulating adder 8 performs the calculation of the sum Z3i, and in the next overflow in counter 1, an additional code of the number equal to

ti -i 22 Si + 1. Under these conditions, overflow signals at the output of counter I are generated upon receipt of those input code pulses, the numbers of which represent the cube values of an integer. The result of the calculation is taken in the form of a number-pulse code from the output of device 10 and can be represented as a parallel binary binary-decimal code, if an appropriate counter is connected to this output.

To ensure the operation of the device without failures, it is necessary to ensure the following time relationships.

The pulse duration of the overflow of the Gi formed at the output of the counter 1 should

ensure steady operation of the used counting triggers. The delay time tj must be chosen from the ratio, where TO is the maximum propagation delay of the logic elements used. Duration of impulse

produced by shaper 7, is determined by the maximum duration of transients in counter 6 and accumulator 8. The pulse repetition period of the input sequence must satisfy

the ratio of t gd s (where t is the maximum duration of transient processes in the counter 1. The device’s speed is determined primarily by the dynamic properties of the logic elements used, and also by the dynamic range of values

Claims (2)

input code. The absolute error of the device does not exceed the unit of the least significant bit of the calculation result and can be reduced by increasing the size of the device, which is substantially less than the error values of the known device. The claims of the device for extracting the root of the third degree, containing two counters, the input of the first of which is connected to the input of the device, the input of the first bit to the installation bus in a single state, and the output to the output of the device, characterized in that accuracy, the accumulator, the trigger, the delay element, the AND element, the OR element and the shaper of i.pulses whose input is connected to the counting trigger input, the first input of the AND element and the output of the delay element, the input of the delay element are entered into the device connected to the first input of the OR element and the output of the first counter, the clocking input of which is connected to the output of the pulse former and the clocking input of the accumulating adder, the input input of the first bit of which is connected to the single output of the trigger and through the serially connected elements AND and OR to the second input of the second counter, the output of the direct code of each i-th digit of which is connected to the information input of the (if 1) -th bit of the accumulating adder, the output of the inverse code of each i-th digit of which from one with ustanovochnb1m clocked input (i + 1) th bit and the first counter. Sources of information taken into account during the examination: 1. Copyright Certificate of the USSR No. 225557, - G 06-F 7/38, 1968. 2. USSR author's certificate No. 359649, cl. G 06 F 7/38, 1969.