SU782166A1 - Binary n-digit pulse counter - Google Patents

Description

The invention relates to a pulse technique and can be used in the design of digital computing device counters. A binary pulse counter is known, each bit of which contains ternary logic elements, an input bus, installation buses at zero and one l. A disadvantage of the known device is its complexity, since each counter of the counter contains seven ternary logic elements. A binary P-bit pulse counter is known, which contains an input bus and bits with three-phase power supply, each of which contains three four-input three-way logic elements and one setting bus to zero and one, in each bit with three-phase clock power output the first ternary logic element is connected to the first and second inputs of the second and fourth inputs of the third logic element, the fourth input of the first of which is connected to the installation bus to zero, the output of the second logic element is connected to the first input the house of the first .troic logic element, the second input of which is connected to the installation bus in the unit, the output of the third ternary logic element is connected to the fourth and first inputs of the first and third ternary logic elements of the next bit, respectively, with three-phase clock power, the input bus is connected to the fourth and first inputs, respectively, of the first and third ternary logic elements of the first discharge with three-phase clock power. In the known device, each ternary four-input logic element performs ternary operations described by the following table TRUE IMG., And -. These operations form a functionally complete system of logic functions and can be implemented on the basis of ternary elements (for example, on G2 Ferrite logic elements) GZ} A disadvantage of the known binary pulse counter is that it has a speed, since the transfer signal in the subsequent gap is formed in two phases of information transfer on the ternary elements of the discharge. . The purpose of the invention is to increase the speed of the counter.

To achieve this goal, a binary n-pulse pulse counter containing an input bus and bits with three-phase clock power, each of which contains three four-input three-way logic elements and installation buses at zero and one, each time with a three-phase clock power output. the first ternary logic element is connected to the first and second inputs of the second ternary logic element, the fourth input of which is connected to the installation bus to zero, and the output to the first input of the first third element of the first three the second input of which is connected to the installation bus in the unit, the output of the third ternary logic element is connected to the first and fourth inputs of the third and first ternary logic elements of the subsequent discharge, respectively, with three-phase clock power, the input bus is connected to the first and fourth inputs of the third and first, respectively ternary logic elements of the first discharge with a three-phase clock power supply, in each discharge with a three-phase clock power supply, the output of the second ternary logic element is connected n with a second input of the third ternary logic gate, the fourth input of the third logic elements trbichnyh even and odd bits of the three-phase power clock sdedineny respectively with tires of the first and second phases of the clock supply.

FIG. 1 shows a diagram of a three-bit binary pulse counter; in fig. 2 - time diagrams of operation of a three-bit pulse counter.

The device will hold together ternary logical elements 1–8, buses 9–11 of installation into a unit of assembled first bit on triple logic elements 1–3, second bit on ternary logic elements 4–6 and third bit on ternary logic elements 7 and 8, the buses 12-14 are set to zero, respectively, of the first, second, and third bits, the input bus 15, the tires 16 and 17, respectively, of the first and second phases of the clock supply. .

The outputs of the ternary logic elements 1, 4 and 7 are connected respectively with the first and second inputs of the ternary logic elements 3, 6 and 8, the outputs of which are connected respectively to the first inputs of the ternary logic elements 1, 4 and 7, the installation buses 9 and 11 are connected

respectively, with the second inputs of the ternary logic elements 1, .4 and 7, buses 12-14 of the installation to zero are connected respectively. With the fourth inputs of the ternary logic elements 3, 6 and 8, the outputs of the ternary logic elements 3 and 6 are connected respectively with the second inputs of the ternary logical elements 2 and 5, the first inputs of which are connected respectively to the fourth input i of the ternary logic element 1 ,. the input bus 15 and the fourth inlet of the ternary logic element 4, the output of the ternary logic element 2, the output of the ternary logic element 5 is connected to the fourth input of the ternary logic element 7, the buses 16 and 17 of the first and second phases of the clock supply are connected respectively to the fourth inputs of the ternary logic elements 2 and 5.

18-20 are timing diagrams of the first, second and third clock supply faae, 21 are timing diagrams of signals on the input bus 15, 22-29 are timing diagrams of signals with correspondingly at the outputs of ternary logic elements 1-8 (Fig. 2)

The device works as follows.

When a pulse arrives at the input bus, the first digit of the counter in elements 1–3 changes its internal state to the opposite. When the counter discharge goes from state 1 to state O, the transfer pulse to the next counter discharge appears at the output of element 2. The presence of feedback allows you to store the result of the addition. The state of the first discharge of the counter is removed from the output of element 3, the second discharge from the output of element 6, and the third discharge from the output of element 8.

When pulses arrive at the installation of buses 12–14 to zero on elements 3, 6, and 8, the pulses of the state of the discharge of the counter compensate, i.e., the counter is reset.

"Q If it is necessary to write the code of a certain number, the values of the digits of the number being written are fed to the unit buses 9-11.

The clock supply system of the counter circuit is three-phase, with each subsequent input impulse of the addendum arriving via bus 15 through the phases (one clock cycle) of information transmission over the circuit elements (Fig. 2, diagram 20). First phase clock pulse

0 reads information from elements 6 and 7, the second phase from elements 1, 2 and 8, and the third phase. From elements 3-5. The pulses arrive at the input bus 15 during the clock pulse of the first

Y5 phase.

The first bus 16 clock supply (phase 1) is connected to the fourth input of element 2, and the second bus 17 clock supply (phase 2) to the fourth input of element 5. This means that these inputs during the clock pulses of the first and second phases of each cycle signals are given, i.e. in the absence of pulses at the first inputs of elements 2 and 5, they are generators of signals of negative polarity.

When the first pulse arrives on the bus 15 by the clock pulse of the first phase of the first clock cycle, according to the logic of the element recorded in the truth table, a positive signal is transmitted to the fourth input of element 1 and to the first input of element 2, and the signal to the fourth input of element 2 is transmitted, the second phase pulse negative signal from element 1 is transmitted to the second input of element 3, the third phase pulse positive signal from element 3 is transmitted to the first input of element 2 and goes to the counter, forming the first digit.

The resulting state of the meter outputs is 001.

When the second yutpuls is received on the bus 15 by the clock pulse of the first phase of the second cycle, the positive signal is transmitted to the fourth input of element 1 and to the first input of element 2, while the signal is transmitted to the fourth input of element 2, the second signal is transmitted by a second phase pulse at the fourth input of element 4 and at the first input of element 5, the signal is transmitted to the fourth input of element 5; the pulse of the third phase transmits the positive signal from element 4 to the first input of element 6.

The pulse of the first phase of the third clock cycle positive signal from the element 6 is transmitted to the first input of the element 4 and to the second input of the element 5 and leaves the counter, forming the second discharge.

The output status of the counter is 010.

Upon receipt of the third impulse through the bus 15 clock pulse of the first phase of the third cycle, the positive:.

The signal is transmitted to the fourth input of element 1 and to the first input of element 2, the signal is transmitted to the fourth input of element 2, the second phase impulses a negative signal from element 1 to the second input of element 3, and the signal to the fourth input of element 5 is transmitted, pulse The third phase positive signal from element 3 is transmitted to the first input of element 1 and to the second input of element 2 and exits the counter, forming the first discharge.

The pulse of the first phase of the fourth cycle, the positive signal from element 6 is transmitted to the first input of element 6 is transmitted to the first input of element 4 and to the second input of element 5 and vspodit from the counter, forming the second discharge.

The output status of the counter is 011.

When the fourth pulse arrives on the bus 15 by the clock pulse of the first phase of the fourth clock cycle, a positive signal is transmitted to the fourth input of element 1 and to the first input of element 2, while the signal to the fourth input of element 2 is transmitted, and the second signal from the second phase is transmitted to the fourth input of element 4, to the first input of element 5, when the signal is transmitted to the fourth input of element 5; the third phase impulses a positive signal from element 5 to the fourth input of element 7.

A negative signal from element 7 is transmitted to the second input of element 8 by a pulse of the first phase of the fifth cycle, and a positive signal from element 8 is transmitted to the first input of element 7 by a pulse of the second phase and leaves the counter, forming the third discharge.

The resultant state of the meter outputs is 100.

Upon receipt of subsequent pulses on the bus 15, the binary counter works in a similar way.

The use of the proposed counter provides, in comparison with the known technical solutions, a twofold increase in the speed of the counter.

table

782166

Claims (3)

1.Sokolov T.N. and others. Ferrite logic elements and nodes of information systems. L., LVIKA them. A.F. MOzhayskogo, 1970, p. 190-192, fig. b4a. " 2. USSR author's certificate number 208347, cl. H 03 K 19/16, 1967. 3. USSR author's certificate cl. H 03 K 23/10, 1978. (for 45 2520231 / 18-21, 20.02. which made the decision to issue an author's certificate) - (prototype).  flumi Takt2 Taktz Tvkt Tapt5 Takte j Nmgguyegi. three-phase source numa / ufl Write +1 Write - / Read About fvufl f / eoHi / e Siting - /