SU879780A2 - Reversible counter - Google Patents

Description

I

The invention relates to computing, can be used to add and subtract impulse sequences.

A reversible counter containing bits is known, the first and second clock inputs of each of which are connected respectively to the addition and subtraction buses, and the transfer and loan outputs are connected respectively to the inputs of the first and second groups of resolution resolution inputs of all other bits, and each bit contains the first, second, third, and fourth elements of AND-NOT, the inverter, the first and second elements of AND-OR-NOT, the first inputs of the first and second elements of PIHE are connected to the outputs of the second and first elements of AND-NOT, respectively, the output of the first element nta AND-NOT connected to the first input of the third INE element, the output of which is connected to the first input of the fourth AND-NOT element, the output of which is connected to the discharge transfer output, the input of the inverter and the first inputs of the first and second groups of inputs of the first element AND-OR , the output of which is connected to the second input of the fourth NAND element and the second input of the second NAND element,

2

the output of the inverter is connected to the output of the discharge loan and the first inputs of the first and second groups of inputs of AND of the second element D-NOT, the output of which is connected to the second input of the third element AND-NOT and the second input of the first element AND-NOT, the second inputs of the first inputs Both the first and second elements are AND-OR-NOT connected to the first

10 clock input of the bit, the second inputs of the second groups of inputs of AND of the first and second elements are AND-OR-NOT connected to the second clock input of the bit, i + 2-e inputs of the first groups of inputs

15 groups of inputs for AND of the first and second elements of the AND-OR-NOT of the K-th digit, where J1 1, ... K are connected respectively to the inputs of the first group of resolution enable inputs of this K-th digit,

20 the second group of inputs for the resolution of the account of which is connected to the -i + 2 inputs of the second groups of inputs on the first and second elements AND-OR-NOT of the same bit i.

25

The disadvantage of this reversible counter is its limited functionality.

The aim of the invention is to extend the functionality

30 reversible counter.

The goal is achieved by the fact that, in a reversible counter, the contents of the bits, the first and second clock moves of each of which are connected respectively with the addition and reading tires, and the transfer and output outputs are connected to the inputs of the first and second groups of inputs, respectively, of all other bits. , and each bit contains the first, second, third and fourth elements AND-NOT, the inverter, the first and second elements AND-OR-NOT, the first inputs of the first and second elements AND-NOT connected to the outputs of the second and first elements AND-H, respectively E, the output of the first element is connected to the first input of the third NAND element, the output of which is connected to the first input of the fourth NAND element, the output of which is connected to the discharge transfer output, the input of the inverter and the first inputs of the first and second groups of inputs of the first element AND-OR-NOT, the output of which is connected to the second input of the fourth element N-NO and the second input of the second element NAND, the output of the inverter is connected to the output of the discharge bit and the first inputs of the first and second groups of inputs AND the second element NAND, the output of which is connected to in the second input of the third element AND-NOT and the second input of the first element AND-NOT, the second inputs of the first groups of inputs on the first and second elements AND-OR-NOT are connected to the first clock input of the discharge, the second inputs of the groups of inputs and on the first and second AND-OR-NOT elements are connected to the second clock input of the discharge, i + 2-e inputs of the first groups of inputs of the AND groups of the first and second elements of the AND-OR-NOT K-th digit, where i 1, ... K are connected respectively, with the inputs of the first group of entries of the permission of the account, this K-th bit, the second group of inputs of the resolution of the cat is connected to the + 2 inputs of the second groups of inputs on the first and second AND-OR-NOT elements of the same bit, the first and second additional AND-HB elements are added, the inputs of the first additional AND-HH element of the HLJ are, respectively, with the transfer outputs of the second and the third bit and the addition bus, as well as with the control bus, which is connected to the input of the second additional INE element, the remaining inputs of which are connected to the inputs of the first, second and third bits, the output of the first additional AND NOT element is connected to the third the two inputs of the second and fourth elements of the NAND, as well as the third inputs of the first groups of inputs of the first and second elements of the OR of the first bit, the fourth input of the first group of inputs of the second element of the AND-OR-NO of which connects with the output of the second An additional item is NOT.

The structural diagram of the reverse counter of the counter is shown in the drawing.

The reversible counter contains bits 1 and first 2 and second 3 additional IS-NOT elements, the first and second clock inputs of each bit 1 of which are connected respectively to the addition and 4 subtract buses 5, the transfer and borrow outputs are connected respectively to the first and second inputs. the groups of inputs for the resolution of the account of all the other bits, and each p of the first 1 contains the first 6, the second 7, the third 8 and the fourth 9 elements NAND, the inverter -10 and the first 11 and the second 12 elements AND-OR-NOT, the first inputs the first 6 and second 7 elements AND-NOT connect with outputs from Secondly, the second 7 and first 6 K-NES elements, the VIXD of the AND-HI element 6, are connected to the first input of the YPE 8 element, the output of which is connected to the first input of the AND-HI element 9, the output of which is connected to the discharge transfer output, the inverter input 10 and the first inputs of the first and second groups of inputs of an AND-OR-HE element 11, the output of which is connected to the second input of the element AND-HE 9 and the second input of the element AND-HE 7, the output of the inverter 10 is connected to the output of the bit and the first the inputs of the first and second groups of inputs on the AND of the second element AND-NOT 12 whose output is connected En with the second input element AND-NOT 8 and the second input element AND-NOT 6, the second inputs of the first groups of inputs on AND elements AND-OR-NOT 11 and 12 are connected to the first clock input of the discharge, the second inputs of the second groups of inputs on And elements AND-OR-NOT 11 and 12 are connected to the second clock input of the discharge, -i the inputs of the first groups of inputs of the groups of inputs for AND elements AND-OR-NOT 11 and 12 of the K-th digit where; -1 1, ".K, respectively, with the inputs of the first group of permission inputs of the account; that of the K-th bit, the second group of inputs of the permission of the account of which is connected to the i + 2 inputs of the second groups of inputs of AND OR OR NOT 11 and 12 of the same size.

The inputs of the AND-NE element 2 are connected respectively to the transfer outputs of the second and third bits 1 and bus 4, as well as to the control bus 13, which is connected to the input of the AND-NE element 3, the remaining inputs of which are connected to the first, second and the third bit 1, the output element AND-NO 11 is connected to the third inputs of the second 7 and fourth 9 elements AND-NOT, as well as the third inputs of the first groups of inputs AND AND-AND-NOT 11 and 12 the first bit and the fourth input of the first the group of inputs for the AND-OR-NOT 12 element of which is connected to the output of the elements that AND NOT,

Reversible counter works as follows.

In the normal binary counting mode, bus 13 is given a signal equal to logical zero, which, entering the inputs of the AND-NOT elements 2 and 3, closes the latter and the outputs of these elements will have a constantly high voltage level. Therefore, the elements AND-NOT 2 and 3 do not affect the operation of the reversible counter, therefore, when pulses are received on bus 4, the counter operates in the summation mode, and when pulses arrive on bus 5, the counter operates in subtraction mode.

In the operation mode of the counter, as a reverse frequency divider modulo 7, the bus 13 is given a signal equal to a logical one. In this case, the element AND-NOT 2 corrects the operation of the counter in the summation mode, and the element AND-NOT 3 in the subtraction mode.

Indeed, let us assume that at the initial moment of time the counter is in the zero state (in the output elements AND-NOT 6, the voltage level is low), and on buses 4 and 5 there is also a low voltage level.

. When a pulse of positive polarity appears on bus 4, the incoming pulses are summed, and after the sixth pulse arrives, the first bit 1 is set to the zero state, and the second and third ones are set to one. Consequently, a high voltage level is established at the outputs of the AND-HE elements of the second and third bits, preparing the AND-HE element 2 to operate.

With the arrival of the seventh addition pulse, a signal equal to a logical zero appears at the output of the AND-NOT 2 element, which closes elements 9 and 12 and sets the first bit 1 to the zero state. Since a signal equal to the logical unit appears at the output of the NAND element 9 of the first bit 1, the second and third bits are set to the zero state, and the counter returns to the initial state. Thus, the input pulse sequence is divided by seven in (summation mode.

In the subtraction mode, at the moment when the counter is in the zero state at the outputs of the inverters 10 of all bits-logical unit, the AND-NE element 3 is opened at the output of this

element appears a signal equal to logical zero, which closes the first group of inputs on the AND-OR-NOT element 12 of the first digit of the counter. Consequently, with the arrival on bus 5 of the subtraction pulse, the second and third bits of the counter are set to one, and the first bit remains in the zero state. Next, with the arrival of the subtraction pulses, the content is subtracted

0 counter and with the arrival of the seventh subtraction pulse, the counter is reset.

This is how the input pulse sequence is divided by

5 seven in subtraction mode.

The introduction of additional elements and new connections in the meter allows to expand the functionality of the device, namely it allows

0 not only to carry out the usual binary account, but also the reverse conversion, of the incoming pulses modulo seven, which is important for a whole class of devices of discrete automation and computing.

five

Claims (1)

1. USSR author's certificate No. 799147, cl. H 03 K 23/02, 04.14.75 (prototype).