SU819970A1 - Multiinput pulse counter - Google Patents

Description

I

The invention relates to computing and can be used to totalize the number of pulses of several stochastic pulse sequences.

A multi-input pulse counter is known, which contains AND elements, OR elements and in each channel pulse counter 1.

A disadvantage of the known technical solution is the low accuracy of the pulse count.

Closest to the proposed multi-input pulse lock, which contains an inverting delay element and AND elements in each channel, triggers and OR elements 2..

A disadvantage of the known technical solution is the low pulse counting speed.

The purpose of P 3 is to increase speed while simultaneously acquiring signals on the input buses of a multi-input pulse counter.

The goal is achieved by the fact that in a multi-input pulse counter containing an inverting delay element

and n pulse counting channels, each of which consists of an AND element, the output of which is connected to the zero input of the first trigger, whose single and zero outputs are connected to the single and zero information inputs of the second trigger, respectively, the clock input of which is connected to the clock bus and to the input inverting delay element, the output of which is connected to the first input element And each of the n channels of pulse counting, and the second and third inputs of the element And each of the n channels of pulse counting are connected corresponding With the single output of the second flip-flop and with the single 1 input of the first flip-flop of this channel, the third input of the AND element of each of the pulse counting channels is connected to the corresponding input bus; account channels

pulses, the unit outputs of the second triggers of each of the n pulse counting channels are connected to the first inputs of the additional elements I, the second inputs of which are connected to the output of the inverting delay element, and the outputs of the additional elements I are connected to the corresponding inputs of the accumulating adder via a parallel counting unit.

The drawing shows a functional diagram of a multi-input pulse counter.

Multi-input pulse counter contains n pulse counting channels, each of which consists of an element AND 1 and triggers 2, 3; inverting delay element 4, block parallel counting units 5, accumulating adder 6, the first group of additional elements And 7, the second group of additional elements And 8, the input band 9, the clock bus 10, the information polling bar 11 and the output band 12.

Multi-input pulse counter operates as follows.

Negative pulses are sent to the input slots 9, which are memorized by triggers 2, in the absence of a clock pulse on the clock pulse bus 10 - triggers 3. When a clock pulse is applied to bus 10, the triggers 3 are blocked and in the time required to set them in some state , determined by the inverting delay element 4, all the triggers 2, which are in the single state, are transferred to the initial zero state, if the corresponding triggers 3 are also in the single state and on the input rails 9 exist negative pulses.

At the same time, information is read in the form of a parallel code from all the triggers, and through the elements of AND 7 this information is fed to the inputs of the block of parallel counting of units 5. This block counts the number of ones in the parallel code, which is fed into the accumulating adder 6 as a binary code. In accumulative adder 6, the number of pulses recorded in a given clock rate is added to the number of pulses recorded in previous clock cycles.

After the end of the clock pulse, the output of the inverting delay element 4 is set to zero voltage level.

If impulses are received at the input 9 at the time of the occurrence of a clock pulse, they are also remembered, regardless of the state of the flip-flops 3, since the And 1 elements are locked and the flashing of the flip-flops 2 is prevented. In the absence of a clock pulse, the triggers 3 assume the state

Triggers 2. In order to get the result from accumulating adder 6, it is not necessary on a bus, in polling 11, to send a pulse, according to which the information content from accumulating adder 6 is transmitted through elements AND 8 to output webs 12.

Thus, in one clock cycle, the number of pulses arriving at the input bands 9 is counted, and this number is added to the number of pulses received at previous clock cycles, whereby the pulse count rate increases n times, where n is the number of input shells.

Claims (2)

1. USSR Author's Certificate No. 513506, cl. H 03 K 23/00, 1974. 2. USSR author's certificate No. 402154, cl. H 03 K 23/00, 1972 (prototype).