SU798833A1 - Multiplying-dividing device - Google Patents

Description

The invention relates to computing and can be applied in digital instruments for processing measurement results (execution; prog daily operations). A device for multiplying the division is known, which contains a pulse generator, two frequency dividers and two counters f 1. The disadvantages of this device are the need to represent one of the factors in the additional code, as well as hardware redundancy. The closest technical. The essence of the invention is a device containing oscillator pulses, a frequency divider, the first And element, two counters, an RS trigger and a group of And elements, a second and third element, and a mode switch, the generator output is connected to the input of a frequency divider; the outputs of the first counter are connected to the inputs of a group of elements And, the s-input of the RS flip-flop is connected to the Start bus, and the output to the first inputs of the second and third elements I. The first counter is summing, and the second subtractor is melting, while the outputs of the generator pulses and a frequency divider connected to the control input are connected via a two-position switch with the second inputs of the second and third elements I, and the outputs of the second and third elements I to the inputs of the summing and subtracting counters, respectively. The disadvantage of this device is hardware redundancy. The purpose of the invention is to reduce hardware costs. The goal is achieved by the device containing a pulse generator, a frequency divider, the first element AND, two counters, two triggers, the first group of elements AND, and the single outputs of the first counter are connected to the information inputs of the AND elements of the first group, the control inputs of which are connected to the output of the first element AND, whose information inputs are connected to the zero outputs of the second counter, the S input of the first flip-flop is the start input of the device, S and R are the inputs of the second flip-flop are respectively input ami dividing and multiplying, data inputs of the first divider and second counters are connected to the

input bus operands, and the outputs of elements AND of the first group are connected to the output of the device, also contains the second and third elements AND, the element OR NOT and the second group of elements AND, while the output of the pulse generator is connected to the first input of the second element AND, the second input of which is connected with the single output of the first trigger, and the third input with the inverse TH input of the first trigger and the output of the element OR NOT the first input of which is connected to the output of the third element AND and the control inputs of the element I. the second group, information inputs cat The first are connected to the single outputs of the second counter, and the outputs from the device output, the single output of the second trigger is connected to the subtracting input of the first counter, the adding input of the second counter and the control input of the third element And, and the zero output to the second input of the second counter the counter and the control input of the first element I, the information inputs of the third element I are connected to the zero outputs of the first counter, the counting input of which is connected to the counting input of the frequency divider and the output of the second of the AND gate, and the carry output of the frequency divider is connected to the counting input of the second counter, and the-output of the first AND element is connected to a second input of OR-NO element.

In the drawing, a schematic representation of the proposed device.

The device contains a pulse generator 1, a frequency divider 2, the first element IZ, the first 4 and second 5 counters, the first 6 and second 7 triggers, the first group of elements AND 8, start input 9, division input 10, multiplication input 11, buses 12-14 operands, device output 15, second 16 and third 17 elements AND, element 1-8, second group of elements AND 19, inputs 20 and 21 of the input information control — first 4 and second 5 counters.

The device works as follows.

Before the start of the multiplication operation, the codes of numbers A & B, which need to be multiplied, are transmitted to the buses 13 and 14. The signal indicated by the multiplication operation is a short negative pulse, which at input 11 sets trigger signal 7 at О and embeds frequency divider 2 and first counter 4. Start signal arriving at input 9 (narrow negative pulse ) sets trigger 6 to state 1; High potential from a single output of trigger 6 arrives at the input of element AND 16 and allows passage through the element

And there are 16 positive pulses from the generator 1, since at the output of the element OR-NOT 18 at the moment there is also a high potential. At the same time, the high potential from the zero output of the trigger 7 is fed to the input of the summation installation in counter 4 and to the input of the subtraction installation in counter 5. The pulses coming from the output of element 16 begin to sum in counter 4 and in the divider counter 2 frequencies. .After passing to the input of splitter 2 a frequency of the number of pulses equal to the value of the code of the number A, a pulse appears at the output of frequency splitter 2,

5 which is fed to the counting input of the counter 5, and one unit is subtracted from the contents of the counter 5, and in the counter 4 at the moment there is a code equal to the value of the number A. After

0 arrival of the next series of pulses from the output element And 16 to the inputs of counter 4 and divider 2 frequency equal to the value of the number A, from the counter code

5, one more unit is subtracted, and to 5, the contents of counter 4 again add the value of the number A.

In a similar way, this operation proceeds further until the code in

Q counter 5 will not be equal to zero, after which the element And 3 is triggered, since at all inputs its high potentials, which also cause a high potential at its output

. (the information inputs of the And 3 element are connected to the outputs of the zero arms of the triggers of the counter 5, and the control input is connected to the output of the zero arm of the trigger 7. The high potential from the output of the And 3 elements enters

0 to the input of the element OR NOT 18 and causes a low potential at its output, as well as to the control inputs 8 of the group of elements AND 8, which allow the passage of the counter code 4 to the output 15 of the device. The low potential from the output of the element OR NOT 18 arrives at the input of the element AND 16 And prohibits the passage through it of pulses from the generator, and

0 also enters the R-input trigger

6 and sets it to the state O. The low potential of the nullity of the trigger 6 also enters the input element And 16, prohibiting the passage through it of generator pulses. On the bus 15 of the device, in time / equal to A-B-d / f (f is the generator frequency), an output code equal to the product of the numbers A and B was received, i.e. .

Before dividing, the dividend is recorded in the counter 4, and the divider is fed through the input 13 of the device to the input of the divider 2 frequency. Operations

Claims (2)

5 divisions are performed in the same way as above, only with this operation, trigger 7 is set to state 1 and gives: once the solution for subtracting from the contents of counter 4 and adding counter 5 to the mu, counter 5 is accumulated in counter 5. When the contents of counter 4 are zero, the element AND 17 is triggered and enables the reading of the counter code through the output element AND 19 to the outputs 15 of the device. The signal from the output of the element And 17, having passed through the element OR-NOT 18, sets in O the trigger 6 and blocks the passage of pulses from the generator through the element 16. At the output 15 of the device, after a time equal to G-1 / f, there will be an output code equal to the quotient of dividing the number of G by the number of A, i.e. . Thus, due to the introduction of an OR-NOT element, an AND element and an AND group of elements, the use of reversible counters, as well as a certain connection of all the elements of the circuit among themselves, it was possible to reduce the number of bits in the second counter by half, which gives an additional gain in hardware. In this scheme, the number of bits in the counter 5 is equal to the number of bits required to store the quotient, while in a known number of bits in the counter 5 is equal to the number of bits required to store the dividend. Claims of invention of a multiplying device,. containing a pulse generator, a frequency divider, the first element And two counters, two flip-flops, the first group of elements And, and the single outputs of the first counter are connected to the information inputs of the elements And the first group, the control inputs of which are connected to the output of the first element And, the information inputs of which are connected with the zero outputs of the second counter, S-ixbd of the first trigger is the device start input, S and R are the inputs of the second trigger. are the inputs of division and multiplication, the information inputs of the de-plumes of the first and second counters are connected to the input buses of operands-, and the outputs of the AND elements of the first group are connected to the output of the device, so that in order to reduce hardware costs, it contains the second and third elements AND, the element OR NOT and the second group of elements AND (the output of the pulse generator is connected to the first input of the second element AND, the second input of which is connected to the single output of the first trigger, and third entry with inv the pc R-input of the first trigger and the output of the element OR NOT, the first input of which is connected to the output of the third element AND and the control inputs of the elements of the second group, whose information inputs are connected to the single outputs of the second counter, and the outputs to the output of the device, a single output The second trigger is connected to the input of the subtraction of the first counter, the input of the addition of the second counter and the control to the digital input of the third element I, and the zero output to the input of the addition of the first counter, the input of the subtraction of the second counter and the control input The first element And, the information inputs of the third element And are connected to the zero outputs of the first counter, the counting input of which is connected to the counting input of the frequency divider and the output of the second element And, the transfer output of the frequency divider is connected to the counting input of the second counter, and the output of the first element And is connected to the second input of the element OR NOT. Sources of information taken into account during the examination 1. USSR author's certificate No. 392495, cl. G 06 F 7/39, 1974 2. USSR author's certificate 271115, cl. G 06 F 7/52, 1969 (prototype).