SU758164A1 - Computer of exponential fuctions - Google Patents

Description

The invention relates to the field of computing and can be used in information processing devices.

A device is known that contains a register, an auxiliary register,

(Ν-1) intermediate result registers and result register £ G}.

A disadvantage of the known device is the impossibility of combining in it the operation of exponentiation with the operations of division and multiplication. The second disadvantage of the known device is its excessive complexity .. ^

The closest in technical essence to the proposed is a calculator of power functions, containing the first counter, the bit outputs of which are connected to the pulse inputs of the 20 elements and the first group, the potential inputs of which are connected to the bit outputs of the second counter, the outputs of which are connected to the first group of inputs of the comparison circuit , the second 25 group of inputs of which is connected to the bit outputs of the register, and the output is connected to the zero input of the trigger, the output of which is connected to the potential input of the AND element whose output is thirty

2

It is connected to the inputs of the first and second frequency dividers, the second group of elements is And £ 2 ^.

However, the known device is overly complex.

The aim of the invention is to simplify the device.

This goal is achieved by the fact that the calculator of power functions containing the first counter, the bit outputs of which are connected to the pulse inputs of elements AND of the first group, the potential inputs of which are connected to the discharge outputs of the second counter, the outputs of which are connected to the first group of inputs of the comparison circuit, the second group of inputs which is connected to the digit outputs of the register, and the output to the zero input of the trigger, the output of which is connected to the potential input of the element I, the output of which is connected to the inputs of the first and The second frequency dividers, the second group of elements And, additionally contains two blocks of subtraction, two blocks of addition, the first input of the first of which is connected to the output of the first frequency divider, and the second input is connected to the output of the first block of subtraction, the first

758164

the input of which is connected to the outputs of elements AND of the first group, and the second to the output of the first addition unit and the inputs of the first counter, the discharge outputs of which are connected to the potential inputs of elements AND of the second group, the pulse inputs of which are connected to the discharge outputs of the second counter, and the output connected to the first the input of the second subtraction unit, the second input of which is connected to the input of the second, _ counter and the output of the second block of supply, the first input of which is connected to the output of the second frequency divider, and the second input is connected to the output m second subtracting unit.

The drawing shows the structure of the device.

rm>

Where

and Ν ^ (ΐ)

^Ν τπ ~

Frequencies ίρ and ί,

N ^ (ί) and N ^ (ί) equations

(eight)

the numbers contained in the counters 1 and 2 and varying in time in the calculation process;

conversion factor counters 1 and 2.

associated with numbers

(9)

It contains counters 1,2, groups of elements IZ, 4, frequency dividers 5, 6, blocks of addition 7, 8, blocks of subtraction 9, 10, trigger 11, element I 12, comparison circuit 13, register 14.

The device works as follows.

Before the beginning of the calculation, the coefficients c with (and ρ are set in frequency dividers 5 and 6, the counters 1, 2 and register 14 record the values of the numbers Υ ^, Υ ^ and X, respectively, “.

20

25

After filing for the trigger 11 of the start signal, element 12 and pulses are opened, the repetition frequencies of which are P _o , are fed to frequency dividers 5

thirty

and 6.

The pulse repetition frequency at the outputs of the blocks of addition 7 and 8 will be equal to:

(one)

(2)

aa

35

40

where ίθ and ί, μ} are the pulse repetition rates at the outputs of subtraction blocks 9 and 10.

Frequencies Gd and () _{0 are} determined by the expressions:

45

40

(3)

(four)

50

where t _and and the pulse repetition rate at the outputs of the elements And groups 3 and 4.

Comparing expression (1) with expression (3) and expression (2) with the expression * 55 eat (4), we get:

(five) ,

(6)

60

Frequencies:

determined by the expression <(7)

g (10)

Substituting the values of frequencies ί ^, ί ₇ and, ί ₃ from expressions (5), (9) and (6),

(10) respectively in equations (7) and (8) and making the obvious transformations, we get

0 (1 'L "/ (.)’

^Η <η

οι 'rm, (th

(eleven)

(12)

Dividing equations (11) into equation (12) and making the separation of variables, we will have:

όΙΝ ₄ (ί) £ όΐΜΐ (1)

Ν _α (1) ' ⁽¹³⁾

At the moment when the number in the counter 2 collapses with the number X recorded in the register 14, the comparison circuit 13 will generate a stop signal, which throws the trigger 11, and the element 12 closes. In this case, the counter 1 will contain the number Ζ.

Having integrated expression (13) with allowance for the limits of variation of the numbers (ι) and N £ (ΐ), we obtain:

? |>? DHTSY (14)

/ sh '

—AH · ⁽¹⁵⁾

Thus, due to the inclusion in the device of two blocks of the regulation and two blocks of subtraction and the introduction of new connections between the elements of the calculator of power functions, two counters are eliminated, thus achieving a significant simplification of the device compared to the known device.

Claims (1)

Claim The calculator of power functions containing the first counter, bit 65 five 758164 6 the outputs of which are connected to the pulse inputs of elements AND of the first group, the potential inputs of which are connected, to the bit outputs of the second counter, the outputs of which are connected to the first group of inputs of the comparison circuit, the second group of inputs of which are connected to the digit outputs of the register, and the output to zero the trigger input, the output of which is connected to the potential input element And, the output of which is connected to the inputs of the first and second frequency dividers, the second group of elements AND, characterized in that, for the purpose of simplification, it contains t two subtraction units, two addition units, the first input of the first of which ** ** is connected to the output of the first frequency divider, and the second input is connected to the output of the first subtraction unit, the first input of which is connected to the outputs of elements And of the first group, and 20 second - to the output of the first addition unit and the inputs of the first counter, the bit outputs of which are connected to the potential inputs of elements AND of the second group, the pulse inputs of which are connected to the discharge outputs of the second counter, and the output connected to the first input of the second subtraction unit, swarm input coupled to the input of second counter and the house ¹ The yields of the second adding unit, the first & stroke of which is connected to the output of the second frequency divider, a second input connected to the output of the second subtractor.