SU496554A1 - Computing device - Google Patents

Description

(54) COMPUTATIONAL DEVICE

one

The invention relates to a computing technique and can be used in information processing devices.

i Known devices that perform arithmetic operations that contain decoders, delay elements, a counter, results, a clock generator, 1 output of which is connected to the first input, the first AND element, the output of which is connected by a separate input of the first counter,: the discharge inputs of which are connected to you. I-moves of the first group of elements And the first inputs of which are connected to the register, and the second inputs - to the output of the first counter and to the separate input of the second counter, the output of which through the first decoder is connected to the second input of the first p & And, the output of which is connected to the first inputs of the second group of elements and directly, and through the first element of the delay, to the first input of the counter of resupats, the outputs of which are connected to the second, red inputs. The second group of elements is And,

the outputs of which are connected to the bit ones: the inputs of the second counter.

Such devices, however, may be separate arithmetic, walkie-talkies.

I The purpose of the invention is to expand the I functionality of the device, I This is achieved by having the device with I hold the add-on) The I piece element, the IOR element and the memory block whose input is connected to the first input of the result counter, i the second input of which is connected to exit; the first input of which is connected to the output

I of the first element And, the second input - with the output of the additional element I and with the separate input of the third counter, the bit inputs of which are connected to the unit, py m, enter the output of the second element through the second decoder so4 with the second

X the first entrance to the optional electrical

: ment And the second input of which through the second delay element is connected to the output of the generator "

; clock puller

 The drawing shows the scheme ycTpoflrGstva .. I It contains counter 1, connected by I paraplelnymi tires with register 2 through a group of elements And in, counters 4, counter 5, ei 6, counter 1, // decoders "delay elements 10, i Jj | aS2i№BrtIT27l3, 14 group of elements. 15, element OR 16, a generator of tactical pulses 17. At turn 18, an argument code is supplied. The device is designed to use Qnx- functions. .as) (- a, Consider the operation of the device on how to calculate the number of terms for the case. The given expression can be written KI (,), A ajA-a., This expression is the basis of the operation of the device. Previously in the counter. 1 and register 2 the value of / X is entered, the value of (1, the counter 7 is the value of Y "in the chpk count, and the memory cells in the memory cells 2) 2 In the general case of coefficients (} x |) 111sherents, the value of d is entered in the counter 4, ; Tick 7 value. And in the cells of the block of the mi coefficients (I. + ft - the memory cell bucket should be equal to 1 p ft + 1 - 2. Counter B G1 edger) is installed / sent to ul. After the codes 4 and 7 are entered into the counters, the decoders of the pulp state 8 and 9 open the elements 12 and 13. The pulses with the frequency / output of the generator 17 enter Reading counters 1 and 7 and the result counter 5 through the element OR 16 At time T TL counter 1 overflows and from its output the signal goes to subtractive counter 4 and overwrites the code from register 2 into counter 1. Over time counter 4 is fixed, and d-coded 8 closes the B item 1.2. Counter 7 is set to zero in time. I-o decoder 9 Close element 13. During time N. -12. T "in counter 5 will arrive -T and in time T" in impulses of t. J. Counter 5 will arrive, - - w. lJ.-J-o pulses, a total of NdH +00 pulses will arrive, since an expression code will be formed, standing in parentheses. As soon as counters 4 and 7 are inserted into O, the signal from element 14 encodes the code from counter 6 through the group of elements 15 and 15 into counter 4, and counter 5 through delay element 11 is reset to 0, simultaneously the signal to block 6 arrives. the code 7 is extracted into the code. Immediately after this, the formation of the expression in the square brackets begins, the result is again transferred to the counter 4. After the output of the code 7 to the code 0, the result of the calculation is deleted from the counter 5, Delay Element 11 Provides moving pulses while simultaneously summing them in the count 5. Formula and 3 problems Computing device containing a counter, detschftoratori, delay elements, a result counter, a clock generator, the output of which is connected to the first input of the first element And the output which is connected to a separate input of the first counter, the bit inputs of which are connected to the outputs of the first group of elements I, the first inputs of which are connected to the register, and the second inputs to the output of the first counter and to the separate input of the second th counter, the output of which is connected through the first decoder to the second input of the first element P and to the first input of the second element. And, the output of which is connected to the first inputs of the second group of elements And the output of which is connected to the first inputs of the second group of elements And directly, and through The first delay element is, to the first input of the result counter, the outputs of which are connected to the second inputs of the second group of elements AND whose outputs are connected to the bit inputs of the second counter, characterized in that, in order to expand the device’s functionality, it contains an additional element, AND, the OR element and a memory block whose input is connected to the first input of the result counter, the second input of which is connected to the output of the OR element, the first input of which is connected to the output of the first AND element, the second input is With the output of an additional element X, a separate input tert its counter, the bit inputs of which are connected to the memory unit, and the output through the second decoder is connected to the second input of the second element I and to the first i input additional electric ment and the second input thereof via a second delay element coupled to an output of the clock.