SU953735A2 - Frequency divider using any integral division factor - Google Patents

Description

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The invention relates to a pulsed field, in particular to a frequency divider, and can be used in automation, computing and radio engineering.

According to the main author. St. No. 843246, a known frequency divider with any integer division factor containing a pulse counter, the counting input of which is connected to the input bus, and the bit outputs, except the first and second, are connected to the decoder inputs, the register and the AND elements, the first inputs of which are the first The C-input of the shift register is combined and connected to the input bus, the second C-input of the shift register is connected to the output of the first element I, the second input of which is connected to the output of the first discharge of the pulse counter, V-input of the shift register is connected to 20 C output d decryptor, D-vkhoyy combined and connected to the output of the second digit of the counter impers, and the output to the second input of the second element And,

the output of which is connected to vcTaHOB04Hbtt | i by the input of the pulse counter 1.

A disadvantage of the known device is a significant amount of power consumption.

The goal of izofeteny is to reduce the consumption of blazing power.

The goal is achieved by adding an additional element I to the frequency divider with any integer division factor, the first input of which is connected to the output of the two-digit decoder, the second input to the output of the last bit of the shift register and the additional installation input c4eiN. pulse, and the output is with the V-input of the shift register.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams that show his work.

The device contains a pulse counter 1 consisting of i in series 2 with high speed and low speed 3 bits 3, elements 4-6 AND, shift register 7, decoder 8. The second input of additional element 6 is connected to the output of the last register bit 7 through the inverter. We consider the operation of this device for the case when the required division factor can be represented as follows, where M is the number corresponding to the formation of the output signal from the decoder and equal to the sum of weights connected to the decoder of the counter bits, starting with the third. The considered division factor corresponds to the connection with the D-inputs of the register 7 of the unit output of the second discharge of counter 1 and the connection with the second input of the element 4 of the unit output of the first discharge of counter 1.; The initial state of the device is described by the following distribution of potentials at the outputs of its constituent elements: counter 1 is completely zeroed, i.e. at the outputs of all its bits there are low potentials. At the outputs of all bits of the register 7 low potentials and on the installation inputs there is an account; chica 1 also has low potentials. Ele: Ment 6 is prepared for opening at the second input, but closed at the first, since the potential of the decoder 8 is low. The low potential, the post to the input V of the shift register I corresponds to its operation in the shift mode, and since its input V is connected to the low potential bus, then by a synchronous signal, after the first C-input) of the bits of the register 7, maintained in the initial state. After the input of the counter 1 M-pulses of the input sequence (Fig. 2o), the output signal is formed from the decoder 8 (Fig. 2S). Because. element 6 is prepared for opening by its second input; then the signal from the output of the decoder 8 passes to L, 2 the input of the register 7 (Fig. 28 The shift register 7 switches to the mode corresponding to the recording of the information supplied to the D At the division factor under consideration, a change in the potential at the D inputs of register 7 from a low level to a high will occur according to (M + 2) impulses of the input sequence. However, the potential changes at its outputs will not occur, since at this moment the output counter break 1 (summing account the low potential is set, and element 4 is closed. By the (M + 3) pulse of the input sequence, a high potential is established at the output of the first discharge of counter 1 and after its termination by a signal from the output of element 4 during all bits of register 7, including In addition, the latter (Fig. 2b) records information supplied to its D inputs, i.e. high potentials. When a high potential appears at the output of the last bit of register 7, the higher bits of counter 1 begin to zero and the signal c decoder output (FIG . 2b). The signal on the V- input of register 7 will change its value significantly faster (Fig. 2d), since element 6 closes when a high potential appears at the output of the last bit of register 7. When a low potential appears on the V2-Input of Register 7, the latter switches to the shift mode and, according to the synchronization signals fed to its first C-input, is gradually filled with low potentials. The low bits of the counter 1 are reset by a signal formed by the output of element 5 according to (M-3 + 1) impulse of the input sequence when the potential of the first discharge of the register 7 has a high potential. Thus, the connection of the output of the decoder 8 to the V input of the register 7 through the input element AND connected to the output of the last register bit of the register will reduce the speed requirements, as well. This means that the consumed power capacity of the higher bits of the counter at the input of the installation and the elements of the decoder. Formula from the obra.teni Frequency divider with any integer division factor By the author. St. No. 843246, characterized in that, in order to reduce power consumption, an additional AND element is introduced into it, the first input of which is connected to the output of the decoder, the second input - with the output of the last digit of the shift register and the additional installation input of the pulse counter. ow, and the output is with the.-shift register input. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 843246, cl. H 03 K 23 / 00.06.08.79.

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Claims (1)

Claim Frequency divider with any integer division factor By ed. St. No. 843246, characterized in that, in order to reduce power consumption, an additional AND element is introduced into it, the first input of which is connected to the output of the decoder, the second input is connected to the output of the last digit of the shift register and the additional installation input of the pulse counter. ow, and the output-s. —the input of the shift register.