SU1425662A1 - Square rooting device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of digital computers and special processors. The purpose of the invention is to increase the accuracy of calculations. The device contains shift register 3, four elements OR 4, 9, 10, 11, element 15, 1K-flip-flop 12, TT-flip-flop 14, RS-flip-flop 25, controlled pulse generator 13, binary counter 21 and serial register approximations 19. New in the device are the HE 5 element, the squaring block 6, the comparison circuit 7, three formers of single pulses 16, 23, 26, the second controlled pulse generator 18, the fifth and sixth elements OR 17, 24 and the element AND-NOT 22. The accuracy of the readings is achieved by calculating the fractional part of the result. 1 il. S (L 4 S SL 05 O5 S

Description

The invention relates to computing and can be used in the construction of digital computers and special processors.

The purpose of the invention is to increase the capacity of the calculations.

The drawing shows the functional diagram of the device.

The device contains a group of information inputs 1, initial setup input 2, shift register 3, first element OR 4, NOT element 5, squaring block 6, comparison circuit 7, start input 8, second, third and fourth elements OR 9, 10 and 11 (respectively), 1K-trigger 12, first controlled pulse generator 13, TT-trigger 14, element 15, first driver 16 one-night pulses, fifth element OR 17, second controlled generator 18 pulses, register 19 successive | approximations, the first group of information outputs 20, binary counter 21, element AND-HE22 | second shaper 23 single-pulse, sixth element OR 24, S-flip-flop 25, third shaper 6 single pulses, 27 signal output at the end of calculations, second GROUP of information outputs 28. The device works as follows. Initial installation pulse

| ; Awarded on input 2, returns the device to its original state. When: the throttle triggers the 3 shift, the pins of the IK- and TT-flip-flops 12 14 sets a high signal level, and the output of the RS-flip-flop 25 is reset to a low level. The high signal level from the direct output of the 1K-flip-flop 12, arriving at the input of the control unit 1 | register of the 3-shift register, transfers it to the parallel loading mode. The trigger pulse, which enters input 8, resets the binary counter 21 to the zero state and, passing through the second element OR 9, with its leading edge, fixes in register 3 the forward binary code of the radicand coming from the information flows 1 group to its data inputs. The first element OR 4 controls the presence of units in the two most significant bits of the root-expression, which is written to the 3 shift register. If units in

5 0 5 0

five

0

five

0

five

Since there is no such bit, then the output of the OR 4 and HE 5 elements, respectively, at the inputs I and K tr of the igger 12 receives low and high levels of the signal. This ensures the switching of the 1K-trigger 12 by the falling edge of the trigger pulse to a low level of the signal at its direct output; this level translates the 3 shift register into the information shift mode towards the higher bits and simultaneously filling the lower bits with zeroes. And the high level of the signal from the reverse output of the 1K-trigger 12 enables the operation of the first controlled oscillator 13. The leading edges of the generated pulses pass through the second element OR 9 shift the information in the shift register 3. At the same time, the TT-trigger 14 switches to the decay of the pulses of the generator 13 divides the frequency of these pulses into two, and the binary counter 21 counts the pulses from the direct output of the TT trigger 14. The number counted by the binary counter 21 is equal to the number of pairs of shifts of the code of the radial expression in register 3. TT deleterious output latch 14 extending through the fourth OR gate 11 is brought 1K-flop 12 in respective levels of signals at its I and K inputs.

It is clear that the return of the direct output of the 1K flip-flop 12 to a high level occurs after that pair of shifts of the radicand, during which one appears in one or both of the high bits of register 3. operation of the controlled generator 13 is prohibited; a high signal level from the output of the first element OR 4 ensures that the last pulse of a series of pulses from the output of the fourth element OR 11 passes through the element AND 15 to the input of the first driver 16 single pulses, which produces a single pulse setting RS- trigger 25 to high state and trigger register 19 successive approximations per cycle of operation.

In the case of zero value of all bits of the radicand expression, all outputs of binary counter 21 are set to one.

p-2, after carrying --- (p-resolution

of the subroutine expression) pairs of code shifts in register 3, which causes the appearance at the output of a low-level element AND-NOT signal 22, which in turn triggers the second formatter 23 single pulses, the pulse from which output passed through the third element OR 10, usjf

feeds a 1k-flip-flop 12 directly into a single state, which stops the information shifts in register 3, and passes through the fifth element OR 17, sets the RS-flip-flop 25 to a single state, and starts the register 19 of successive approximations to the work cycle.

If in one of the two most significant bits of the radicated expression after it is loaded into register 3 there is one, the switching of the 1K-flip-flop 12 does not occur, and the trigger does not start after the high level of the signal at the output of the first element OR 4 passes through the element 15 and with its decay, the first generator of 16 single pulses is started, the pulse produced by which passes through the fifth element OR 17 sets the RS flip-flop 25 and starts the register 19 of successive approximations for an operation cycle in which oc the square root is directly extracted, but not from the original argument, but from a number equal to the product of the original argument by a factor of 4, where m is the number of pairs of shifts of the initial argument in register 3, counted by binary counter 21.

For any values of the radical expression, the square root extraction process is as follows. Switching the RS flip-flop 25 to a high signal level enables the second controlled generator 18 to operate. On the leading edge of the first of its pulses, code 011 ... 111 is set on the bit outputs of the sequential approximation register 19, and its output on the end of the conversion is set to in high state. The leading edge of the pulse from the generator 18 starts the squaring block 6, the result from its output goes to the 7-comparison circuit, where it is compared with that shown from the shift register 3

0

by number. If the code from register 3 is greater, then at the output of the comparison circuit 7, one is entered — otherwise, zero. The leading edge of the second pulse coming from the generator 18, the result of the comparison is fixed in the highest bit of the register 19 consecutive approximations. At its bit outputs, either code 001, .. 111 or code 101 ... 11 1 is set. At subsequent clock cycles, the subsequent bits of register 19 are set in successive approximations. At the end of the conversion circuit, the output of the signal of the end of the conversion of register 19 is reset to a low level, which ensures the launch of the third generator 26 of single pulses, which the pulse generated by passing through the sixth element OR 24 resets the RS flip-flop 25, and having received the output signal 27 at the end computing

5 shows the fact of readiness of the result of calculations at the information outputs 2P and 2B of the device. The code on the first group of information outputs 20 is an integer equal to the product of the actual result by 2, and the code on the second group of information outputs 2B is equal to t. The number determines the number of shifts of the result towards the lower bits in order to normalize it. Such a representation of the result allows one to obtain a fractional part of it. In this case, the calculated number of bits of the fractional part is m.

0

five

40

45

50

55

Claims (1)

Invention Formula A square root extractor containing a shift register whose information inputs are the information inputs of the device, first to fourth OR elements, AND element, 1K flip-flop, TT-flip-flop, RS-flip-flop, first controlled generator of 1 pulses, binary counter, the zeroing input of which is the device startup input, the serial approximation register, the bit outputs of which are the first group of information outputs of the device, about which, in order to improve accuracy, it is a squaring block, three single pulse pullers, a second controlled pulse generator, a comparison circuit, a NOT element, a fifth and a fifth elements OR, a NAND element, a input zero reset register are entered. the input of the initial installation of the device and is connected to the first f, the inputs of the third and sixth elements The UTPL clock input of the shift counter register and the second input of the exact and first group of information outputs of the device are connected to the bit outputs of the sequential approximation register, the information input of which is connected to the output of the comparison circuit. Direct and inverse outputs of the TT-trigger are connected respectively to the binary input ha is connected to the output of the second element OR, the first inputs of the second and fourth elements OR and the binary counter reset input are connected by the device Start input, the second input of the second OR element is connected by the output of the first controlled pulse generator and the TT trigger trigger input, the installation input to 1 of which and the control input of the shift register are connected to the direct input of the 1K-trigger, the inverse output and | the installation input in 1 of which is connected respectively to the input of the first controlled pulse generator and the output of the third element of the IPI, and the clock input is connected to the input of the fourth OR element and the first input of the AND element, the second input of which is the input of the element NOT and the 1 input of the .1K trigger connected to the output of the first element OR, the first and second inputs of which are connected to c) 1 inputs of the two higher bits of the shift register, the bit outputs of which are connected to the first group of inputs of the comparison circuit, the second d |) of which inputs are connected to the discharge you to exit the block squaring, data inputs of the correct element OR, the output of the element is NOT connected to the K input of a 1K trigger, the output of the element AND through the first driver of a single pulse connected to the first input of the fifth OR element, the second input of which and the second input of the third OR element are connected to the output of the second single pulse generator, the input of which is connected to the output of the NAND element whose inputs are connected to the binary outputs of the binary counter and to the second group of information outputs of the device, the output of the computational end of which is connected to the output of the third single pulse generator and to the second input of the sixth OR element, the output of which is connected to the reset input of the RS flip-flop, the direct output of which through the second controlled pulse generator is connected to the control input of the squaring unit and the clock input of the sequential approximation register, the start input of which and the RS flip-flop setup input are connected to the output of the fifth OR element, and the entrance of the third single pulse generator.