SU1488791A1 - Square root extractor - Google Patents

Description

The invention relates to computing and can be used both independently and as a special processor in combination with digital computers to increase the performance of the entire system.

The purpose of the invention is the expansion of functionality due to the additional calculation of the function of the form X = A'LGv ¹ with a simultaneous increase in accuracy.

The drawing shows a block diagram of the device.

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contains the shift register, the six elements OR, the element NOT, the block is up-. squared, comparison circuit, DC-trigger, two controlled pulse generators, TT-trigger, element And, three drivers of single pulses, a register of successive approximations, a binary counter and Eztrigger. New in the device are five elements OR, shift register, element. NOT, multiplication unit, comparison circuit, register of successive approximations, CC-trigger, two controlled pulse generators, two AND elements, two single pulse generators, short-circuit trigger, binary with counter and binary adder. Expansion of functionality is achieved by calculating the values of a function of the form X = A / ^ B ¹ , where X, A and B are, respectively, the desired result, the first and second operands.

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The device contains the first and second groups of information inputs 1 and 2 of the device, input 3 of the initial installation, input 4 start the device, block 5 extraction square root,. block 6 division, the first 7 and second 8 groups of outputs of the device, output 9 "End of conversion" of the device, moreover, the square root extraction block 5 contains the first shift register 10, elements OR 11-17, And 18, controlled generators 19 and 20 pulses, element NOT 21, quad

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22, comparison circuit 23, L <-trigger 24, TT-trigger 25, KZ-trigger 26, first binary counter 27, sequential approximation register 28, drivers of 29-31 single pulses, division unit 6 includes the second shift register 32, the second element NOT 33, multiplication unit 34, second comparison circuit 35, second register 36 consecutive approximations, elements OR 37-40, elements AND 41 and 42, binary counter 43, binary adder 44, third and fourth controlled generators 45 and 46 pulses , 15 shapers 47 and 48 single pulses, ίΚ-trigger 49, KZ-trigger 50 „

The device works as follows. 20

The impulse of the initial installation, fed through the input 3, brings the device to the initial state. In this case, the second binary counter 43, the first 10 and second 32 shift registers 25 are reset, the direct outputs of the first .24 and second 49 <TC-flip-flops and TTTrigger 25 are set to a high signal level, and the outputs of both KT3 triggers 26 and 50 are reset to 30 low level.

High levels of the signal from the direct outputs of LC-flip-flops 24 and 49, acting on the control inputs of the first and second registers of the shift of ~ 10 and 32, respectively, translate them into parallel information loading mode,

A trigger pulse, which enters input 4, sets 27 on all outputs of the first binary counter: · dd high levels of signals and, darocho through the second element OR 12, with its leading edge fixes in the first shift register 10 a direct binary code · of the B root, arriving from the first group of information inputs 2 devices on its data inputs

The first element OR 11 controls the presence of units in the two star bits of the root-expression, written in the first shift register 10.

If there are no units in these digits, then the output of the OR 11 and NOT 21 55 elements, respectively, to the inputs of the K K LKtrigger 24 is low and high levels of signals. This ensures that the LK-trigger 24 is switched by the falling edge of the trigger pulse to a low level at its direct output. . This level translates the 10 shift register into the information shift mode towards the high-order bits while simultaneously filling the low-order bits with logical zeros. A high signal level from the reverse output of the LC-trigger 24 allows the operation of the first controlled generator of 19 pulses. Leading edges of pulses produced by them, passing through the second OR gate 12, shift data in the shift register 10 _of This CT-flop 25, switching to the decay generator 19 pulses, divides the frequency of these pulses by two, and the contents of the binary counter 27 'is reduced by the number of pairs of code shifts of the radicapulism in register 10. Pulse spikes from the reverse output of the TT trigger 25, passing through the fourth element OR 14, lead <TC trigger 24 to the signal levels at its L and K inputs. Consequently, the return of the direct output of the PC trigger 24 to a high level occurs after that pair of shifts of the radicand, during which one appears in one or both of the high bits of the registers 10. In this case, the operation of the controlled generator 19 is prohibited, and the high level of the signal from the output of the first element OR 11 ensures that the last pulse of a series of pulses from the output of the fourth element OR 14 passes through the first element AND 18 to the input of the first driver 29 single pulses, which generate a single pulse that sets the first CG-trigger 26 in a high state and starting the first register 28 successive approximations on the work cycle,

In the case of the zero value of all bits of the radicate expression, all the outputs of the binary counter 27 are set to the zero state after holding η = -and ~ _3 (n

the bit depth of the root expression) pairs of code shifts in register 10, which causes the appearance at the output of the seventh element OR 17 of a low level signal, which triggers the second driver of 30 single pulses. The impulse it forms,

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passing through the third element OR 13, sets the direct output of the LS trigger 24 to a single state, thus stopping information shifts in register 10, and, passing through the fifth element OR 15, sets KTrigger 26 to a single state and starts the register 28 of successive approximations cycle of work.

If there is a unit in one of the two most significant digits of the radicap after it is loaded into register 10, the trigger does not switch .ΙΚ-trigger 24 by the drop of the trigger pulse: a trigger itself after the high signal at the output of the first element OR 11 passes through the element 18 and its recession starts the shaper 29, the pulse produced by which sets the short-circuit trigger 26 into one state and starts the register 28 of successive approximations to the work cycle in which the extraction is carried out of the square root but not from the original arguments, of number equal to the product of the original argument by the coefficient ^P 4 where η pairs of initial argument number of shifts in the register 10.

The process of extracting the square root is as follows.

Switching CB-trigger 26 to a high signal level enables the second controlled generator of 20 pulses. On the leading edge of the first pulse generated by it, the code 011 ... 1Π is set at the digit outputs of the register of 28 successive approximations, and its signal about the end of the conversion is set to high, the falling edge of the pulse from the generator 20 starts the squaring block 22, the result is its output enters the comparison circuit 23, where it is compared with the 10 number presented from the register. If the code from register 10 is greater, then a unit appears at the output of comparison circuit 23, otherwise zero. The leading edge of the second pulse coming from the generator 20, the result of the comparison is recorded in the highest time * row of the register 28 successive approximations. At its bit outputs set either code 001,., 00.111, or code 101 ... 111. On subsequent clock cycles, the subsequent bits of the register of 28 successive approximations are set in the same way. At the end of the conversion cycle, the output of the signal about the end of the conversion of the register 28 is reset to a low level, which ensures the launch of the third shaper 31 of single pulses, which the pulse generated by passing through the sixth element OR ^ throws a short-circuit trigger 26.

He also indicates the end of the extraction phase of the square root of the source argument B, the code on the bit outputs of register 28 is a direct code of an integer equal to the product of the actual result by .2, and the code on the bit outputs of the counter is (---- ~ ¹ "n). Such

presentation of the result makes it possible to calculate the fractional part of the root in the case of zero high-order digits of the original argument B »The number of digits of the fractional part will be equal to

The division is carried out according to the following method

The code of the dividend A, digit capacity of which

equal to ---, shifts the shift register toward the higher digits by the number sh, equal to the number of shifts of the dividend, until the highest significant unit in its most significant digit appears. In addition, the resulting shift code is fed to the first group of inputs of the second comparison circuit with a constant offset in

digits, which is achieved by multiplying the shifted code of the dividend A by a constant factor of 2 ^g

The divider calculated at the first stage is already shifted towards the higher digits by n. Thus, in block 6 of division, the quantity

A 2 ™ 2 ^ ' ¹ }

----------------, the code of which

enters the first group of information outputs 7 devices, and

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the second group of information outputs 8 is formed by the value code

- V - п), + ш], characterizing the number of shifts of the result towards the lower digits, necessary for its normalization "

The operation of the division unit is as follows.

The pulse from the output of the shaper 31, passing through the ninth element OR 38, with its leading edge, fixes in the second shift register 32 the direct binary code of the dividend A, fed through the second group of information inputs 1 of the device ₀ If zero appears at the highest bit output of the register 32 after recording, then the back edge of the pulse from the shaper 31 of the second PC-trigger 49 is reset to a low level on the direct output, which ensures the switching of the register 32 to the shift mode “A high level e of the reverse output of the PC-trigger 49 allows operation that of the third controlled generator 45 pulses o On the leading edge of the pulses produced by it, the code of the dividend is shifted in register 32 in the direction of the higher digits. When a unit appears at the higher digit output of register 32 at inputs I and K of trigger 49, conditions are created for its switching, which occurs as the pulse decays from generator 45, which prohibits further shifts of the dividend. In this case, the counter 43 counts the number of shifts made, m, and the last pulse of the 45 series of pulses generated by the generator passes through the third element I 42 and starts the fourth driver 47 of the single pulses with its falling edge. The single impulse that he forms triggers the second register of 36 successive approximations per cycle of operation,

In the case of a zero value of the dividend, all the outputs of the counter 43 are set to one state after

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carrying t = - 1) shifts

which causes the appearance of a high signal level at the output of the second element AND 41 and the output of the tenth element OR 40, the last pulse from the generator 45 passes through the third ele25

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ment 42 and its rear front launches shaper 47 "

If, after loading the dividend into register 32, the unit is immediately set to its higher bit output, switching of the PC flip-flop 49 does not occur, and part of the pulse from the driver 31 passes through the third element I 42 and starts the driver 47 with its falling edge. The pulse starts the register 36 on the work cycle and switches the second short-trigger 50 to a high signal level, which allowed the fourth controlled generator 46 pulses. On the leading edge of the first pulse generated by it at the discharge outputs of a register of 36 successive approximations

the code is set to 011 ,,. 111, and its output signal about the end of the conversion is set to a high state.

The leading edge of the pulse from the generator 46 starts the multiplication unit 34, the result from its output goes to the comparison circuit 35, where it is compared with the number arriving at its first group of information inputs. If the code on the first group of inputs is larger, then a unit appears at the output of the comparison circuit 35, otherwise zero »The leading edge of the second pulse coming from the generator 46, the comparison result is fixed in the high-order bit of the register 36 successive approximations.

At its bit outputs set either code 001 .., 111, or code 101. ,, 111. On the subsequent clock cycles, the remaining bits of the register of 36 successive approximations are set in the same way. At the end of the conversion cycle, the output of the signal at the end of the conversion of register 36 is reset to a low level, which ensures the start of the fifth shaper 48 single pulses, which the pulse generated by passing through the eleventh element OR 40 resets the short-trigger 50, and by its appearance at the output 9 of the device about the fact of readiness of the result of calculations at information outputs 7 and 8 of the device.

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The code on the first group of information outputs 7 is an integer equal to the product of the actual result

2 ^, 2 ^ "')

on ---- 2nd ---- " ^{and K} ° D ^{on the} second group of information outputs 8 is equal to £ (-" 1 ^{- n} ) ⁺ , This value

is determined by the adder 44 and determines the number of shifts of the result in the direction of the lower digits in order to • normalize it. Thus, the division, like the extraction of the square root, by the proposed device is performed with great accuracy by determining the fractional part of the result.

Claim

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A device for extracting the square root containing the first shift register, from the first to the sixth elements OR, the quad, the first element is NOT, the first and second controlled pulse generators., The first comparison circuit and the element And, the first register of successive approximations, the first LC-trigger, short -trigger, first binary counter, TT-trigger and three forms-. a single pulse generator, the information inputs of the first shift register being the first group of information inputs of the device, the initial setup input of which is the reset input of the first shift register and connected to the first inputs of the third and sixth OR elements, the start input of the device connected to the first inputs of the second and fourth elements OR , the clocking input of the first register's shift is connected to the output of the second element OR, the output of the fourth element OR is connected to the clock input of the first LC-trigger and ne the first input of the first element AND, the second input of which, the input of the first element NOT and the L input of the first LCtrigger are connected to the output of the first OR element, the inputs of which are connected to the outputs of the two most significant bits of the first shift register, the bit outputs of which are connected to the inputs of the first group of the first comparison circuit , the second group of inputs. which is connected to the digit outputs of the quad, information inputs

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which is connected to the bit outputs of the first register of successive approximations, the information input of which is connected to the output of the comparison circuit, the output of the element is NOT connected to the K input of the first LC trigger, the installation input is "1 ⁿ and the inverse output of which is connected respectively to the output of the third OR element and the input of the first controlled pulse generator, the output of which is connected to the second input of the second element OR and the clocking input of the TT-trigger, the input of which is set to "1" and the control input of the first shift register Points to the direct output of the first LC trigger, and the inverse output to the second input of the fourth element OR, the output of the first element AND connected to the input of the first driver of single pulses, the output of which is connected to the first input of the fifth element OR, the second input of which is the second the input of the third element OR is connected to the output of the second single pulse generator, the output of the fifth element OR is connected to the start input of the first register of successive approximations and the installation input of the first short-circuit trigger, the reset input and the direct output of the cat The op is connected respectively to the output of the sixth OR element and the input of the second controlled pulse generator, the output of which is connected to the control input of the quadtro clock input of the first register of successive approximations, the output of which through the third single pulse generator is connected to the second input of the sixth OR element, characterized in that in order to extend the functionality due to the additional calculation of the function of the form X ------ while

increasing the accuracy, the second shift register, the multiplication unit, from the seventh 'eleventh elements OR, the second element NOT, the successive approximation register and LC-trigger, the second comparison circuit, the third and fourth controlled pulse generators, the second and third elements AND , fourth and fifth single formers

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pulses, second short-circuits and a binary counter, a binary adder, and the first binary counter is made subtractive, with the installation input in ”1" and the clock input of the first binary counter connected respectively to the device start input and direct output of the TT trigger, inputs and output of the seventh of the OR element are connected respectively to the information outputs of the first binary counter and the input of the second single pulse generator, the information inputs of the second shift register are the second group of information inputs of the devices TWA, the initial setup input of which is connected to the zeroing inputs of the second shift register, the second binary counter and the first inputs of the eighth and eleventh OR elements, the clocking input of the second shift register is connected to the clock input of the second LC-trigger and the first input of the third AND element and the ninth element OR output whose first input is connected to the output of the third single pulse generator, and the second input and clocking input of the second binary counter to the output of the third controlled pulse generator, the input It is costly connected to the inverse output of the second LC trigger, the direct output of which is connected to the control input of the second shift register, the bit outputs of which are connected to the inputs of the first group of the second comparison circuit, except for the senior and group of low-order bits, the inputs of which are connected to the common bus of the device, inputs the second group of the second comparison circuit is connected to the bit outputs of the multiplication unit, and the output is connected to the information input of the second register of successive approximations, the installation input to "1" of the second LC trigger is connected to the output ohm of the eighth element OR, the second

the input of which is connected to the output of the second element AND and the first input of the tenth element OR, the second input of which, combined with the L input of the second LC trigger and the input of the second element NOT, is connected to the output of the higher digit of the second shift register, the output of the second element is NOT connected to K -the input of the second LC-trigger, the information outputs of the first binary counter connected to the inputs of the first group of the binary adder, the inputs of the second group of which and the inputs of the second element And are connected to the information outputs of the second binary counter, you One of the tenth OR element is connected to the second input of the third element AND, the output of which is connected via the fourth single pulse generator to the trigger input of the second sequential approximation register and the input of the second CG trigger, the reset input and the direct output of which are connected to the eleventh element output and the input the fourth controlled pulse generator, the output of which is connected to the clock input of the second register of successive approximations and the control input of the multiplication unit, in The first and second groups of which are connected respectively to the bit outputs of the first and second successive approximation registers, the bit outputs of the last of which are the outputs of the first group of the device, the outputs of the second group of which are connected to the bit outputs of the binary adder, the second input of the eleventh element OR is connected through the fifth single driver pulses to the output "End of conversion" of the second register of successive approximations and is the output of the "End of conversion" device about

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Claims (1)

The device for extracting the square root refers to computing, technology and can be used both autonomously and in combination with a digital computer as a special processor. The aim of the invention is to enhance the functionality due to the additional calculation of the function of the form X = А / ^ В ^1, with simultaneous increase in accuracy. Device