SU955208A1 - On-line storage checking device - Google Patents

Description

The invention relates to computing, namely, storage devices.

A device for controlling RAM is known, comprising a counter, a register, a decoder, a control unit and a control unit. This device allows cyclic monitoring of RAM memory.

The disadvantage of the device is low memory monitoring efficiency.

Closest to the present invention is a device for monitoring RAM, containing a control unit, a first counter and a number register connected to the device output buses, a counting trigger, a driver, an AND element, a second counter for counting subcycles, a third counter, a half adder, main and additional 1yatatopami. A monitored memory block C2 is connected to the device.

The disadvantage of this device is the low reliability of the control, since the Rain and Address code tests do not provide a complete check of the RAM, in particular, of the interconnections of the cells.

The purpose of the invention is to increase the reliability of the control.

The goal is achieved by the fact that in the device for controlling RAM, containing a number register, the outputs of which are outputs of the device, the information inputs of the number register are connected to the outputs of the switches of the first group, the first

10 formational inputs to which are connected to the output of the Imatopor field, the second information inputs of the switches of the first group are connected to the outputs of the corresponding switches of the second group,

15 control inputs of the switches of the first group are connected to the corresponding outputs of the control unit, the first input of the half-adder is connected to the trigger output and the first input of the one-oscillator,

The output of which is connected to the first input of the element I, the output of the element I is connected to the input of the first counter, the outputs of which are the address outputs of the device, one input of the trigger 25 is connected to the corresponding output of the first counter, the control inputs of the switches of the second group are connected to the outputs of the second counter, and the information inputs of the switches

30 second group connected to the outputs

the third counter, the second input of the half adder is connected to the corresponding output of the third counter, the second inputs of the element I, the trigger and the impeller, as well as the inputs of the second and third counters are combined and connected to the corresponding output of the control unit, the delay element is first input connected to it the output of the one-shot, the first and second outputs of the delay element are connected respectively to the third and fourth information inputs of the switches of the first group, the second input of the delay element li ne to the output control unit.

The drawing shows a block diagram of a device for monitoring RAM.

The device contains a control unit 1, the output 2 of which is connected to the input of the register 3 numbers consisting of flip-flops 4, the first counter 5, trigger b, one-shot 7, delay element 8, element 9, switches 10 of the first group, half-adder 11, switches 12 of the second group, the second counter 13, the third counter 14, the operational memory block 15. The first counter 5 has a width of n, where A is the number of addresses. It ensures the formation of an address code. The one-vibrator 7 provides for the negative edge of the signal. Delay element 8 provides information shift by one cycle after each sub-cycle for generating test type 1 and O type. The second counter 13 is designed for counting sub cycles. The third counter 14 provides the formation of a test of the type. The address code. Its width is n + 1.

Consider the operation of the device in the Rain mode. The source of information recorded in register 3 is the half adder 11. When started up in control unit 1, a clock pulse sequence is generated. In the first subcycle, the counters 5 and 14 work synchronously from the same clock cycles of block 1. At the same time, at the inputs of the half adder 11, the code is the same, and its output is low, corresponding to the code O record for all memory addresses. At the end of the first sub-cycle with the one-shot 7, the falling edge of the signal from the output of trigger b is extracted and a single pulse of advance into counter 5 is prohibited (in element 9). As a result, the second by; :( cycle in counter 5 ends by one clock cycle (equal to the period of calls ) later than in counter 14, and the half adder will record the unevenness at the end of the second subcycle. Therefore, in the second subcycle, in all memory addresses, except the last

codes O will be recorded, and in the latter - code 1. At the end of the second sub-cycle, exactly one more pulse of progress into the counter 5 will be prohibited. Accordingly, the unevenness will be fixed in the last two addresses of the third sub-cycle where code 1 will be recorded. Thus, the block 15 operational memory,; filled in the first subcycle with all zeros, is filled in the units below, i.e. The process of raiding units is typical for Rain test. When the A sub-cycles pass, the codes at the input of the half adder 11 will be inverse and the entire block 15 will be filled with units. In the next steps, the sub-cycles in the same way, starting with the last address, the code of the units is replaced by the number of zeros. After 2A subcycles, the entire test period ends.

Consider the operation of the device in the formation of the test type Address Code. In this case, the control signals from block 1 are connected to the inputs of register 3 and the number of outputs of counter 14 (via switches 12 and 10).

The operation of the switches 10 is similar to their operation in the Rain mode, except that the source of information is not the half-adder 11, but the counter 14, and the counters 13 and 14 differ in frequency, equal to

new -jj-. In this case, the code of the number, recorded in block 15, will change with each address and each next sub-cycle in the address code will start with different code combinations, which will ensure a dynamic shift of information on the sub-cycles. Due to the presence of switches 12, "controlled by counter 13, it is possible to connect to the corresponding register bits 3 the number of different bits of counter 14 in different subcycles. This achieves the alignment of the dynamics of work of different bits.

Consider the operation of the device in the formation of the test type of Running 1 and O. In this case, the control signals from block 1 are connected to the inputs of the register 3 outputs of the element 8 delay (phase switches. 10). During the first subcycle, the rear edge of the signal from the output of counter 5 (via trigger 6) is allocated to all addresses of block 15 with the single vibrator 7, and the first advance pulse to counter 5 is deducted. The signal delayed by one cycle of the reverse frequency the output of the delay element is fed to the inputs of the register 3 (through the switches 10). Delay element

There may be, for example, a D-trigger. Consequently, in the second subcycle, code 1 will be written into the first address of block 15, and O will be recorded in the rest. In this case, record 1 to the first address

happens over. If 5 did not have a delay per clock, then after recording 1, O would be written to the same address. At the end of the second subcycle, it is prohibited to advance the second pulse to the counter 5. In the first

the output address of block 15 is the code O, and the second BQ is 1. The remaining addresses are written zeros. Thus, the RAM block 15, filled with zeroes in the first subcycle, 5 starting from the first address, will be filled with a running unit, which is typical for the test of Running 1 and O. When the A + 1 subcycles pass, the code will be written in the last address and in the others - O. During the first A + 1 subcycles, the signals on the control buses allow the signal through the switches 10 to pass from the direct output of the delay element 8 a p.,. the following A + 1 subcycles - with inverse. During A + 2 sub cycles, the output bus of block 1 is set to 1, the first pulse of progress is disabled, and all the addresses of block 15 are written 1. For the next A sub cycles the same way, starting from the first address, will be written to all addresses code running zero. The timing diagram for the second part of the test is not shown, as picture 35 is similar to the first part. After 2A + 2 subcycles, the full test period is completed.

Thus, the proposed device allows to increase the reliability40 of the control due to the fact that, along with tests such as Rain and Address code, the device allows to check the working memory with the help of the test running 1 and 0, allowing more fully to check the mutual interference memory cells.

Claims (2)

1. USSR author's certificate number 497640, cl. G 11 C 29/00,. 2.Avtorskoe svide7 Soviet Union 547837, cl. G 11 C 29/00, 1975 (prototype).