SU541169A1 - Quarter root extractor - Google Patents

Description

one

Isooretation is related to computing and can be used in the construction of specialized computing devices and functional information transducers.

A device for extracting a fourth degree root, containing a register, four adders, a counter, blocks of elements And delay elements and constructed according to a general scheme for reproducing a function, Reverse polynomial, by the finite difference method, is known.

The disadvantage of this device is a large amount of hardware costs for both calculating the directly function and for entering the initial conditions into the register and the adders.

It is also known a square root extraction device containing a drive, a register, a pulse shaper, AND elements, a trigger, and delay elements and operating in the mode of comparing the square of a number of consecutive odd numbers with the value of the root expression.

This device has a limited number of tasks, because it allows you to extract only the square root of a sequence of pulses, and to extract a fourth-degree root from a parallel code, you must use a parallel code to serial converter, which

leads to a significant decrease in the speed of the device.

The closest technical solution to the present invention is a fourth-degree root extraction device comprising a counter, the OUTPUT of which is connected to the first input of the first block of elements I, the output connected to the first input of the first adder, the output of which is connected to the first input of the second block of elements And, the output of the connected to the first input of the second adder, the output of which is connected to the first input of the third block of elements And, the output connected to the first input

the third is an accumulator, the output of which is connected to the inverse input of the trigger, the direct input connected to the input bus, and the direct output to the input of the pulse former, the output of which is connected to the output

bus and the input of the first delay element, the output connected to the output of the second delay element.

The purpose of the invention is to increase the speed and simplify the device.

This is achieved by the fact that in the proposed device, the output of the pulse driver is connected to the second inputs of the first and third adders and the first and third blocks of elements I, the output of the first delay element is connected to the third input of the first adder and the counter input, the output of the second delay element connects to the second inputs of the second the adder and the second block of elements I.

The drawing is a schematic diagram of the proposed device.

The device contains a counter 1, the first 2, the second 3 and the third 4 adders, the first o, the second 6 and the third 7 blocks of the elements And, the first 8 and the second 9 elements of the zaderlsky trigger

10 and pulse shaper 11 (input bus 12, output -13).

The device works as follows.

In the initial state, in the third adder 4 there is an additional code of the number x, from which the fourth degree root must be extracted, and in the counter 1, the first 2 and second 3 adders contain zero codes. When a pulse is applied to the input bus 12, the trigger 10 is transferred to the single state on the direct input and starts the pulse shaper I. When the First pulse arrives from the pulse shaper

11 in the lower bits of the first 2 and third 4 adders, written one by one. In addition, the first adder 2 through the first block of elements And 5 is transferred twice (shifted by one bit to the left) the contents of counter 1, and the third adder 4 - twice (shifted by one bit to the left) the contents of the second adder 3 through the third block of elements And 7. The same pulse of the pulse driver I, passed through the first delay element 8, ensures the execution of the second cycle of operation of the device, during which a unit is added to the second bit of the first adder 2, and one unit is added to the two lower bits of the counter 1 i.e. 3. Pass through the second delay element 9, the pulse from the output of the pulse generator 11 performs the third cycle of operation of the device, in which the second adder 3 adds a unit to the low-order bit and doubled (shifted by one bit to the left) content: its first adder 2 through the second block of elements And 6.

Upon receipt of the next pulse of the pulse former 11, all three cycles of operation of the device described above are used. The pulses from the pulse generator 11 to the output bus 13 are made until the third adder 4 overflows, the overflow pulse of which enters the inverse input of the trigger 10, brings it to the zero state, which, in turn, turns off the driver pulses I. Pa output bus 13 passes the number of pulses y,

equal to the root of the fourth degree in Yx)

from number X.

The proposed device in comparison with the known devices, including the prototype, has the following advantages:

- higher speed, determined by three cycles, instead of four;

-Lower hardware costs for one block of And elements and one delay element;

- more simple connections between adders 2 and 3, as well as counter 1 and adder 4.

Claims (1)

Invention Formula Device for extracting the fourth root the degree containing the counter, the output of which is connected to the first input of the first block of elements And, the output connected to the first input of the first adder, the output of which is connected to the first input of the second block elements And, the output connected to the first input of the second adder, the output of which is connected to the first input of the third block of elements And, the output connected to the first input of the third adder, the output of which is connected to the inverse trigger input, the direct input connected to the input bus, and the direct output - with the input of the pulse former, the output of which is connected to the output bus and the input of the first element delay, the output connected to the input of the second delay element, characterized in that, in order to improve speed and simplify the device, the output of the pulse shaper is connected to the second inputs of the first and third adders and the first and third blocks of elements And, the output of the first delay element is connected to the third input the first adder and the input of the counter, the output of the second delay element is connected to the second inputs of the second adder and the second block of elements I. five