SU595728A1 - Arrangement for raising binary number to the fourth power - Google Patents

Description

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The invention relates to digital computing and can be used in the construction of computing devices and functional information converters.

A device for raising a binary number to the fourth power of numbers received by a sequential code is known, containing a register of numbers, registers of the first, second and third blocks, adder trn, multipliers and groups of elements I.

The disadvantages of this device include a large amount of hardware and the impossibility of erecting into the wall the numbers represented by the unitary code.

The closest to the technical solution of the invention is a device for raising a binary number to the fourth power, containing a binary counter, first, second and third adders, four groups of elements I. And for the first time the inputs of elements AND of the first group are connected to the outputs of the binary counter, and the outputs of elements AND of the first groups - with the inputs of the first adder, the outputs of which through the second and third groups of elements I are connected to the first and second grounds of the inputs of the second adder, outputs connected through the elements AND the fourth soil to the input Dami third adder, the first and second delay elements and the input bus bar connected to the input of the first delay element, the output of which is connected to the input of the second delay element.

However, such a device has a relatively low speed and a large amount of equipment, due to complex connections and the presence of three delay elements.

The purpose of the invention is to increase the speed and simplify the device.

This is achieved by the fact that in the device the input bus is connected to the lower-end inputs of the first and third adders and with the second inputs of the AND elements of the first and fourth groups, the outputs of the first and second delay elements - with the second inputs of the AND elements of the second and third groups, respectively; the delay element is connected to the input of the binary counter, and the output of the second element to the input of the lower bit of the second adder.

The block diagram of the device is shown in outline.

It contains a binary counter 1, the first 2, the second 3 and the third 4 adders, a group of elements And 5-8, the elements 9, 10 delayed and the input pin 11.

The device works as follows. The initial state of counter 1 and adders 2-4 is zero. In the first cycle, the pulse impinges on the input pin AND, adds to the contents of the adder 2 double (shifted by one :: discharge left) code from binary counter I, to the contents of the adder 4 doubled (shifted by one bit to left ) code from adder 3 and adding a low-order unit to adders 2 and 4. In the second cycle, a low-order unit is added to the input bus to the binary counter 1 and doubled (with a shift and one bit to the left) the code of the adder 2 to the contents of the adder 3, and in the third cycle -

one unit of small bit in the heatmaker 3 and a long-time (with a shift of two times ws: -iO) code

iTOp;

to soder / iaiMOMy sum 3.

After three clocks in adders 2 and 4, form 1 cp 1, its code is square and fourth, respectively, of the sequence of pulses, post} -invial spike 11, the parallel code of the sum of which accumulates in double counter meter 1.

The operation of the device is illustrated in npn.:crom, given in the table.

The device allows you to reduce the amount of equipment the device by eliminating

delay element and the connection between the outputs of the first group of elements And 5 and the inputs of the adder 4, which greatly simplifies the adder 4. In addition, it provides an increase in speed, so in the known devices each input pulse is processed in four cycles, and in the proposed device three cycles i.e. a performance gain of 25%.

Claims (1)

Invention Formula A device for raising a binary number to the fourth degree, containing a binary counter, first, second and third adders, four groups of elements AND, the first inputs of elements AND of the first group are connected to the outputs of a binary counter, and the outputs of elements AND of the first group are connected to the inputs of the first adder, the outputs of which through the second and third groups of elements And are connected to the first and second group of inputs of the second: II fij „.J. adder, the outputs of which through the elements of the fourth group are connected to the inputs of the third adder, the first and second delay elements and the input bus connected to the input of the first delay element, the output of which is connected to the input of the second delay element, characterized in that, in terms of speeding up and simplifying the device, the input bus in it is connected to the low-voltage inputs of the first and third adders and the second inputs of the first and fourth elements groups, the outputs of the first and second delay elements are connected to the second inputs of the elements of the second and third groups, respectively, the output of the first delay element is connected to the input of a binary counter, and the output of the second element is LCD - to the input of the least significant bit of the second adder. lib / f I - 1 4f K: . -, -.