SU1504801A1 - Variable divider of pulse recurrence rate - Google Patents

Description

The invention relates to a pulse and computer technology and can be used in pulse frequency synthesizers, multiplying-dividing devices. The purpose of the invention is to improve the performance of the device by

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reduce energy consumption without reducing performance - is achieved using as the second and subsequent counters elements with reduced speed and power consumption, while the speed requirements for the second and subsequent counters are reduced by 2-times, where k is the counters width, compared to the speed of the first counter that determines the maximum input repetition rate, and power consumption is determined mainly by the first counter and the elements entered. The controlled pulse repetition frequency divider contains the source of codes 1 of a given division factor, counters 2-1 - 2-p, made as a group of digits of the counting triggers, input bus 3, output bus 4, KB-trigger 5 and the OR element 6. 2 Il.

1504801 A1

(rig. 1

1504801

The invention relates to a pulse and computing technology and can be used in pulse pulse frequency synthesizers, multiplying-dividing devices and other devices of instrument-making and computing technology.

The purpose of the invention is to improve the performance of the device by reducing power consumption without reducing performance by providing the possibility of using as the second and subsequent counters elements with reduced performance and power consumption with

The speed requirements for the second and subsequent counters are reduced by 2 ^to 2 times, where k is the width of the counters, compared to the speed of the first counter, which determines the maximum input repetition rate, due to which power consumption is determined mainly by the first counter and the entered elements.

FIG. 1 is a block diagram of a controlled pulse frequency divider; in fig. 2 - time diagrams of his work.

The controlled pulse repetition frequency divider (Fig. 1) contains the source 1 of codes of a given division factor, counters 2-1 - 2-p pulses, made in the form of groups from to the bits of the counting trigger with the inputs of a parallel installation,

connected to source 1 codes. The inverse transfer outputs P of the second and subsequent counters 2-2 to 2-p are connected to the corresponding counting inputs (-1) of the subsequent counters 2-3 to 2-p, the high-order output of the first counter 2-1 is connected to the counting input of the second counter 2- 2, the input bus 3 is connected to the counting input of the first counter. In addition, the device contains an output bus 4, a short-circuit trigger 5 and an element OR 6. The inverse transfer output of the last counter 2-n is connected to the inverse reset input of the short-trigger 5, the output of which is connected to the inverse write enable inputs of the second and subsequent counters 2-2 - 2-p and to the first input of the element OR 6, the second input of which is connected with the inverse transfer output of the first counter, the inverse input of the recording resolution of which is connected

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thirty

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45

eO

is connected with the output bus 4, the output of the element OR 6 and the inverse input of the short-circuit trigger 5.

The divider works as follows.

The input sequence pulses (Fig. 2a) from the input bus 3 (Fig.1) arrive at the counting input of the first counter 2-1, operating in the subtraction mode, with the result that pulses are generated at the output () _and most-significant discharge, whose frequency To is determined by the coefficient recalculation of the CP (capacity) of the first counter 2-1 and the input frequency Е _о , coming from the input bus 3 (Fig. 26):

g - ·

’CP

Pulses from the inverse transfer output of the first counter 2-1 frequency

ν Кп

? ₁ , the duration of which is - times

exceeds the period of the input pulse sequence from the input bus 3, goes to the counting input of the second counter 2-2, while the pulse state decreases the code state of the second counter 2-2 by one and when the counter 2-2 reaches the zero code state in the pause between pulses on its counting input at the inverse transfer output of the counter 2-2 forms a logical zero level (Fig. 2c), which, acting on the counting input of the subsequent counter, at the end of its transition from the zero to one state translates the next with etchik a new code state, less than the previous unit. Thus, at the first transfer output of the last counter 2-p, the logical zero level is set at the moment when the counter codes 2-2 - 2-p accept zero states and the second zero output of the first counter of the first counter sets the logical zero level (FIG. 2d).

The low level of the pulse from the inverse transfer output of the last counter 2-p, acting on the inverse reset input of the CK-flip-flop 5, sets a low potential at its output (Fig. 2e), which, acting on the inversion inputs of the second 2-2 and subsequent counters 2-3 - 2-p, writes codes in them, set150480

the source of 1 codes, updated at their inputs, then the level of the logical unit is set at the inverse transfer output of the last counter 2-p. In this case, the conditions for resetting the trigger 5 are removed and the low level signal arrives at the first input of the element OR 6. However, at the second input of the OR 6 element, there is a high level signal from the inverse transfer output of the first counter 2-1, which comes through the OR 6 element to the inverse input of the short-circuit trigger 5. Through the number of input frequency clock, determined by the code on the information inputs of the counter 2-1 , at its inverse transfer output a low level signal appears, which arrives at the second input of the element OR 6. Since the first input of the element OR 6 also has a logic zero level from the output of the short-circuit trigger 5, then a low level signal appears at its output I, which goes to the output bus 4 of the device, to the inverted input of the recording resolution of the first counter 2-1 and to the inverse input of the KTtrigGger 5 installation, cocks the short-circuit trigger 5 and enters the code from the information inputs of the first counter 2-1 to the triggers of this counter ₀ Steady at the same time, a high voltage level at the output of the KZ-flip-flop 5, acting on the resolution inputs for recording counters 2-2 2-p, terminates the process of recording the code arriving at their information inputs, and sets the level of the logical unit at the output of the OR 6 element. The output pulse on the output bus 4 of the device is completed, the code is copied from the information inputs of the first counter 2-1 and its triggers are terminated, and the short-circuit trigger 5 becomes sensitive to a new reset pulse in the new cycle of operation. The pulse duration at the output 4 of the device is determined by the total response delay of the element OR 6 when the output signal from the state of logical zero to the state of logical one and the transfer signal of the first counter 2-1 when entering the parallel code, as well as the switching time of the short-circuit 5 in unit state. Thus, with a total signal delay time in the first counter 2-1, the element

OR 6 and short-circuit 5 less than half the repetition period of the input pulses, the output of the device 4 pulse appears (Fig. 2g) every time when the code state of the first counter 2-1 becomes zero, and the second and subsequent counters 2-22- n are in the state of entering into them the initial code of the source of 1 codes, after their code state has assumed the zero state. Since the pulse duration at the counting inputs of the second and subsequent counters 2-2 - 2-p is equal to half the period of the pulse sequence at the output of the high-order discharge of the first counter 2-1 (Fig. 2b):

„_ Кп _ _η_ ί βχ

^{1 and} ~ 2p7 ^_ 2 ''

then the speed requirements of the second 2-2 and subsequent counters are 2-3 '2-n in К п = 2 times less than for the first counter 2-1,

Claims (1)

Claims The controlled divider of the pulse repetition frequency, containing the source of codes of a given division factor, input and output buses, η pulse counters, information inputs of which are connected to the outputs of the source of codes of a given division factor, the counting input of the first pulse counter connected to the input bus, inverse transfer outputs ί-χ pulse counters - to the counting inputs (ί + 1) -χ pulse counters, where ί = 2- (η-1), and the recording resolution inputs from the second to the r th pulse counters are interconnected, o Considered by the fact that, in order to reduce power consumption without decreasing speed, a short-circuit trigger and an OR element are entered into it, the output of which is connected to the output bus and to the inverse input of the short-circuit trigger, the inverse reset input of which is connected to the inverse transfer output of the ηth pulse counter, and the output - to the inverse input of allowing the recording of the second pulse counter and the first input of the OR element, and the high-order output of the first pulse counter is connected to the counting input of the second pulse counter, the inverse output n Renos - to a second input of the OR gate, and the inverted write enable input with the output bus. 1504801