SU997038A1 - Device for parity check of parallel code - Google Patents

Description

The invention relates to computing and can be used to detect errors in the transmission and storage of information in the Binary code. A device for monitoring parallel binary parity code is known, which contains a shift register, a trigger, an AND element group, delay element.

The speed of this device is small, since the number of shift pulses required for parity is determined by the number of the upper register in which logical 1 is written. V

The closest to the present invention is a device for monitoring a parallel binary code containing a trigger, an AND element and a shift register, a bit that contains a trigger whose single input is the information input of the device, the first additional AND element and the OR element, and the single output the trigger of each bit is connected to the first inputs of the corresponding first element of the AND element and the OR element, the input of the code.

Secondly, it is connected to the information inputs of the trigger of the subsequent discharge, the information input of the trigger. the most significant bit is connected to the second input of the element OR of the given bit; and with a logical zero signal input. the device, the output of the OR low-order element is the register output and is connected to the first input of the AND element, the second input of which is connected to the second inputs of the additional AND elements and to the synchronizing input of the device, the output of the AND element is connected to the counting input of the trigger 15, whose output is output device, and the outputs of the additional elements And are connected to the clock inputs of the flip-flops of the corresponding bits.

20

A disadvantage of the known device is its low speed. Although the number of shift pulses is equal to the number of logical units of the code being checked, with a large number of

25 units to check parity code will take considerable time.

The aim of the invention is to improve the speed of the device.

The goal is achieved by

30 that a device for controlling parallel binary code on parity containing the first element AND, the parity trigger, the shift register, each bit of which contains a trigger, the element AND, and the element OR, and the synchronizing input of the device is connected to the first inputs of the elements AND all bits and with the first input of the first element AND, the output of which is connected to the counting input of the parity trigger, the output of the parity trigger is the output of the device, the output of the AND element of the register is connected to the trigger synchronization input corresponding to the current bit of the shift register, the direct information inputs of the device are connected to the single inputs of the flip-flops of the corresponding bits of the shift register, the installation input of the device is connected to the zero input of the high bit trigger of the shift register and to the first input of the element OR of the same bit, the output of the trigger of each bit the shift register is connected to the second input of the element And and the first input of the element. OR of the same bit, the output of the element OR of each bit of the register, the shift except the younger one, is connected to the D input of the trigger and the second input of the element OR the subsequent bit of the register, the shift, the output of the element OR the lower bit of the shift register is connected to the second input of the first the element And, put the second and third elements And and the delay element. and in each digit of the shift register an additional element And, an additional element OR and an additional trigger are introduced, and the device clock input is connected to the first inputs elements AND of all bits of the shift register and through the delay element with direct inputs of the second and third elements AND whose outputs are connected respectively to zero inputs of additional triggers of shift register bits, inverse information inputs of the device are connected to single inputs of additional triggers of corresponding bits of shift register , the installation input of the device is connected to the 0 input of the additional trigger of the start of the shift register and to the first input of the additional element OR it on the same bit, the output of the additional trigger of each bit of the shift register is connected to the second input of the additional element AND and the first input of the additional element OR of this bit, the output of the additional element OR of each bit of the shift register, except the youngest, is connected to The O-input of the additional trigger and the second input of the additional element OR the subsequent discharge of the shift register the outputs of the element OR and the additional element OR the lower bit of the shift register are connected respectively to inverse inputs The second and third elements And, the third input of the first element And is connected to the inverse input of the third element And, the output of the additional element And each bit of the shift register is connected to the IN synchronization input of the additional trigger of the corresponding bit. In the proposed device, a separate simultaneous shift of logical 1 and O of the code being tested is performed. This invention can be used to control codes with an even number of bits. If the code being tested contains an even number of bits, then in this code the parity attribute of the units coincides with the value of the parity attribute of zeros: if the number of ones is even, then the number of zeros is also even, and if the number of ones is odd, then the number of zeroes . Since, in the general case, the code being tested contains a different number of ones and zeros, then counting fewer bits of the same name shortens the verification time — the parity code, i.e. improves performance. The drawing shows a diagram of a device for checking a 4-bit parallel binary parity code. The device contains a shift register 1, consisting of bits 1, ..., l., Each of which contains a trigger 2, the first element AND 3, the element OR 4, d; an additional trigger 5, an additional element And 6, an additional element OR 7, as well as the first element I. 8, the parity trigger 9, the second element AND 10 and the third element AND 11g the delay element 12, the synchronization input 13, the setup input 14, the forward information inputs 15 and the inverse information inputs 16. The setup inputs of the trigger 2 and additional trigger 5 of the senior bit Ij register 1 are connected to the mouth novochnym input device 14. In each category de l, ...,. register 1 single inputs of trigger 2 and additional trigger 5 are connected to the corresponding direct information input 15 of the register and inverse information input 16 of the register, the installation inputs of the trigger 2 and 5 are connected respectively to the first inputs of the elements OR 4 and 7, the second inputs of which are connected respectively to the right my input trigger 2 and the inverse output of the additional trigger 5, the specified connection points are connected respectively to the second inputs of the elements 3 and 6, the first inputs of which are connected to the synchronizing the input 13 of the device, and the outputs, respectively, with the sync inputs of the flip-flops, 2 and 5.

The setup input 14, which has the potential of logical O, is connected to the setup inputs of trigger 2 and additional trigger 5 of the highest bit of 1 register.

. The output of the element OR 4 of the previous bit is connected to the installation input of the trigger 2 of the subsequent bit. The output of the element OR 4 low-order bit 1d is connected to the input of the first element AND 8. The output of the additional link OR 7 of the previous bit is connected to the installation input of the additional trigger 5 of the subsequent bit. The output of the additional element OR 7 lower order is connected to the third input, the first element AND 8, the first input of which is connected to the synchronizing input 13 of the device, and the output to the input of the trigger 9 of parity.

The outputs of the elements or 4 and 7 of the lower bit 1. are connected respectively to the inverse inputs of the second 10 and third 11 elements And, the direct inputs of which are connected to the output of the delay element 12, the input of which is connected to the synchronous input 13. The output of the second element 10 is connected to - reset inputs of all triggers 5, and the output of the third element And 11 with the reset inputs of all triggers.

The installation of all the triggers to the initial zero state is not shown on the drawing.

In the initial state, all the triggers are set to the zero state. In this case, the direct outputs of all triggers 2 and all additional triggers 5 are set to logical O.

From the output of the elements OR 4 and 7 of the younger bit of 1 l, logical O are received at the second and third inputs of the element 8, and logical 0 arrives at the counting input of the parity trigger 9.

Consider the parity check of code 1110.

When applying direct and inverse code values, respectively, to direct 15 and inverse 16 information inputs of the device, the triggers are set in the following state: flip-flops 2 bits 1, l H and flip-flops 5 bits 14-3 unit state; trigger 2 bits I, and triggers 5 bits 1, l. 1-j, to the zero state.

A trigger 2 or 5, set to one, permits an AND 3 or B element to pass a clock pulse through it from input 13.

Trigger 2 or 5, which is set to the zero state, prohibits an AND 3 or B element for the passage of a clock pulse through it.

The unit potentials from the forward paths of the trigger points 2 bits 1, 1, 1 and trigger 5, bit 14, through the corresponding elements OR 4 and 7, arrive at the second and third inputs of the And 8 element, respectively, allowing it to pass clock pulses from the input 13.

The unit potentials from the outputs of the elements OR 4 and 7 of the lower order 1 enter, respectively, the inverse. The inputs of the second and third elements AND 10 and 11, prohibiting them from passing the pulses from the delay element 12.

The first clock pulse performs the following actions: having passed through the AND 8 element, changes the state of the parity trigger 9; writes the zero level to the trigger 2 bits 1, which blocks the element AND 3 of this bit, rewrites the unit level in the triggers 2 bits 1 and l, j, writes the zero level, to the trigger 5 bits 1, which blocks the additional element And 6 of this bit to pass through a neg. sync pulse.

At the inverse input of the third element AND 11 from the output of the element OR 7 low-order bit C, a zero level is received, which allows the third element AND 11 to pass through the clock delayed in the delay element 12 of the sync pulse.

The minimum delay time is determined by the switching time of the flip-flops 2 and -5.

After the delay time, the first sync pulse passes through the third element 11 and enters the reset of the flip-flops 2 of all bits, setting them to the zero state. The state ± rigger 9 parity indicates that the code being checked is odd. To check the code, 1110 needed a single clock sync pulse versus three clock cycles needed for the prototype test.

The positive effect of using this device is to improve the speed of determining the parity of a parallel zoic code by simultaneously performing a parity check of logical 1 and.o. Since in the general case the number is different, the checking of a smaller number of the parity bits of the same name is unambiguous with the parity check of the code being checked significantly improves the speed.

Claims (2)

Invention Formula Device for control of parallel binary stake on parity, co. the first element is AND, the parity trigger, the shift register, each discharge of which contains a trigger, the AND element and the OR element, and the device sync / lowering input is connected to the first inputs of the AND elements of all bits and the first input of the first element AND, the output which is connected to the counting input of the parity trigger, the output of the parity trigger is the device output, the output of the AND element of each shift register is connected to the trigger input of the trigger of the corresponding shift register bit, the forward information inputs of the device Connected to the single inputs of the trigger of the corresponding bits of the shift register, the installation input of the device is connected to the D input of the high bit trigger of the shift register and to the first input of the IL element of the same, the output of the trigger of each bit of the shift register is connected to the second input of the And element and the first the input of the OR element of the same bit of the output of the element OR of each bit of the shift register, except for the lower one, is connected to the D input of the trigger and the second input of the element OR the subsequent bit of the shift register, the output of the element OR low bit The register of the second unit, And, is characterized by the fact that, in order to increase the speed f, the second and third elements AND and the delay element are introduced into the device, and the additional element AND, the additional element OR are entered into each digit of the shift register. an additional trigger, the synchronizing input of the device is connected to the first inputs of additional elements AND of all bits of the shift register and through the delay element to the direct inputs of the second and one third of its elements AND, whose outputs are connected according to For example, with zero inputs of additional triggers of all bits of the shift register, inverse and 1 | formation inputs of the device are connected to single inputs of additional triggers of the corresponding bits of the shift register, the device setup input is connected to 0-6 of the high shift register and from the first EXP1 additional element OR of the same bit, the output of the additional trigger of each bit of the shift register is connected to the second input of the additional element AND and the first input of the additional An additional element OR of the same rar yes, the output of the additional element OR of each bit of the shift register, except the younger one, is connected to the D input of the additional trigger and the second input of the additional element OR of the subsequent bit; the shift register, the outputs of the element OR and the additional element OR, the least significant bit the shift register is connected respectively to the inverse of the inputs of the second and third and And, the third input of the first element And is connected to the inverse input of the third element And, the output of the additional element And each bit of the shift register is connected to the synchronization input of the additional trigger of the corresponding bit. Sources of literacy, In the examination during the examination 1. USSR author's certificate 746530, cl. G О F 11/10, 19вО. 2. USSR author's certificate of application No. 2865062 / 18-24, cl. G About F 11/10, 1980 (prototype).