SU1670788A1 - Frequency divider of sequence of pulses with variable fractional coefficient of division - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation devices, computing and measuring equipment. The purpose of the invention is to increase the reliability of operation by introducing impulses 8, an inverter 9, an element OR 10, a delay element 11 and forming new functional connections into the counter of the counter. In addition, the divider contains a clock pulse generator 1, counters 2, 4, 6 pulses, a comparison element of codes 3, registers 7, 13 of memory, buses 14, 15, 12 and 5 first code, second code, control and output, respectively. 2 Il.

Description

yo

About xj

About vj 00 00

Schig1

The invention relates to a pulse technique and can be used in automation devices, computing and measuring equipment.

The purpose of the invention is to increase the reliability of operation.

Figure 1 shows the electrical block diagram of the device; 2 shows timing diagrams for his work.

The device contains a clock pulse generator 1, the output of which is connected to the counting input of the first counter 2 pulses, whose information outputs are connected to the first group of information inputs of the code comparison element 3, the second group of information inputs of which are connected to the information outputs of the second counter 4 pulses, and the output output bus 5, the third pulse counter 6, the information inputs of which are connected to the information outputs of the first: memory gist 7, fourth pulse counter 8, inverter 9, elements OR 10, a delay element 11, the input of which is connected to the output of the code comparison element 3, and an output to the counting input of the third pulse counter b, the transfer output of which is connected to the counting input of the second counter of 4 pulses, moreover, the recording enable inputs of the second and third counters 4 and 6 pulses are connected to the output of the element OR 10, the first input of which is connected to the control bus 12, and the second input to the transfer output of the fourth counter of 8 pulses, the counting input of which is connected to the output of the inverter 11, the input of which is connected to the output of the delay 11 and to the reset input of the first counter 2 impulses, the information inputs of the second counter 4 pulses are connected to the information outputs of the second memory register 13, and the information inputs of the first and second memory registers 7 and 13 are connected respectively to the first and second code points tires 14 and 15 of setting the fractional and integer part codes of the division factor.

The device works as follows.

On code buses 14 and 15, the source code of the division factor is set. The division ratio is determined for a full cycle of dividing counter 8 as

Ifo

K K1 m

K1 - code installed on the bus 15; K2 - code installed on the bus 14; m - the capacity of the counter 8.

The integral part of the division factor K1 takes a value from 1 to (2n-2), where n is the width of counter 4, the width of counter 2 corresponds to the size of counter 4.

The fractional part of the division factor K2 is set by the required accuracy of the synthesized frequency and determined by the digit of counter 6 and

counter 8.

The Start command from bus 12 through the element OR 10 goes to the control inputs of counters b and 4. This command records the source code of the division.

counters b and 4. Counter 2 counts the frequency of the reference frequency generator 1. When comparing the code from the output of counter 2 with the code recorded in counter 4, the code comparison element 3 generates a pulse, which

arrives at the output bus 15. This same pulse, having passed through the delay element 11, is fed to the counting input of counter 6 and through the inverter 9 to the counting input of counter 8, i.e. added to the fractional part

the source code of the division is recorded in counter 8. He then zeroed counter 2 and the cycle repeats. Formation of output pulses with a period of the whole part of the source code occurs until

the counter 6 is filled and the transfer pulse to the counter 4 is not formed. After that, the division factor will change and the follow-up period of the synthesized frequency will change accordingly. Frequency generation with a modified period will occur until counter 8 is filled and generates a source code restore impulse. The frequency with the initial pulse following period is synthesized using the recovered code.

When divided by an integer, the division factor correction does not occur as a result of restoring the original division code in the counter 6 pulses from the output of the counter 8,

Claims (1)

The invention The pulse frequency divider with variable fractional fractional ratio, containing the reference frequency generator, the output of which is connected to the counting input of the first pulse counter, the information outputs of which 5 are connected to the first group of information inputs of the code comparison element, the second group of information inputs of which are connected to the information inputs of the second pulse counter, and the output to the output bus, the third pulse counter, information inputs of which are connected to the information outputs of the first memory register, that, in order to increase the reliability of operation, a fourth pulse counter, an inverter, an OR element, a control bus, a delay element, whose input is connected to the output of the code comparison, and the output is the counting input of the third pulse counter, the transfer output of which is connected to the counting input of the second pulse counter, and the write enable inputs of the second and third pulse counters are connected to the output of the OR element, the first input of which is connected to the bus I1 and 11 ii 111 I ii I I 11 iiiiiii 11 iii and i and ii. i 11 i i and p 11 and 11 MI i and and them and m 1 .. 1 nnnrijri pp p ppppppppp n n Sri ppppppppppppppp J 7 I-I I-I P I-I I-II-I P. P 1-I P I-1P I-01-I P I-I P P P 0 The second input is connected to the transfer output of the fourth pulse counter, the counting input of which is connected to the output of the inverter whose input is connected to the output of the delay element and to the reset input of the first pulse counter, the second memory register is also entered, and the information inputs of the second pulse counter are connected to information outputs of the second memory register, and information inputs of the first and second memory registers are connected respectively to the code bus to set the code of the fractional part of the division factor and the second code bus installation code integer part of the division factor. P P about