SU1663607A1 - Digital function generator - Google Patents

Abstract

The invention relates to computing and is intended to form a normalizing function code and sine, cosine and arctangent codes. The purpose of the invention is to increase the speed of the digital function generator. The digital function generator contains the first 1 and second 2 adders, multiplier 3, the first memory block 4, the block 5 elements EXCLUSIVE OR, the element NOT 6, the first control input 7, the code input 8 of the address setting constant, the first switch 9, the first element AND 11 and the inputs of the first 19 and second 20 bits of the operation code, input - output 10 of data, elements AND 12 - 15, the second memory block 16, the second 17 and third 18 switches, the first 21 and second 22 elements EXCLUSIVE OR, register 23, element OR 24, block 25 elements OR, second control input 26 and clock input 27. The goal is achieved Due to the introduction of AND 12-15 elements, memory block 16, switches 17 and 18, EXCLUSIVE OR elements 21 and 22, register 23, OR element 24, block 25 OR elements. 2 Il.

Description

The invention relates to computing and is intended to form a (2 + n) -discharge code of the normalization function from an address code, a (1 + n) -discharge direct sine or cosine code to (2 + n) - the discharge angle code varying from O to 2 n () radians, and the n-bit code of the arctangent by the n-bit code of the argument 6 0, (), where n is the size of the reduced code of the angle or argument of the arctangent, and can be used to build a specialized microprocessor computer (SMW), for example, for a device displaying information radar.

The purpose of the invention is to increase the speed and reduce the hardware costs of the digital generator of functions.

FIG. 1 shows a block diagram of a digital function generator; Fig. 2 shows timing diagrams of signals at a clock input, at the second control input, at the first control input of the generator, and at the output of the OR element.

The generator (FIG. 1) contains the first 1 and second 2 adders, multiplier 3, first memory block 4, block 5 elements EXCLUDING OR, element NOT 6, first control input 7, address code input 8 of the constant setting, first switch 9, code input-output 10, first 11, second 12, third 13, fourth 14 and fifth 15 elements AND, second memory block 16, second 17 and third 18 switches, input 19 of the first and input 20 of the second code of the operation code , the first 21 and second 22 elements EXCLUSIVE OR, register 23, element OR 24, block 25 elements OR, second control input 26, clock in code 27, code outputs 28 and 29, formed by the bit outputs of the high and low bits of the adder 2, respectively, and code output 30, the first 31, the second 32, and the third 33 outputs of the register 23.

We denote at the inputs and outputs of the generator and its nodes by P, F, and And, respectively, potential signals, codes, and inverse pulses so that after each of these letters the number of the generator input, for example, P7, F8 and E27, means O

or 1 at input 7, the code at input 8 and inverse pulses at input 27, respectively, or the generator node number, for example, W, F9 and I24 indicate potential signals for the overflow output of adder 1, code

from the code output of the switch 9 and the inverse pulse at the output of the element 24, respectively.

In addition, we denote by F28 P19F28 the code on the second code input of the switch 9 and the first code input of the switch 17, F17 P13F17-code on the address code input of the memory block 16, F30 P13FZO - the code on the address code input of the memory block 4, FNF F4F16 - the code of the normalizing function on the first code input of the switch 18 (where F1b means the code formed by the corresponding two bits of the F16 code), FTF P322P32F1 is the code, the trigonometric function on the second code input of the switch 18, (P1) and (P2) are the content (code) of the first and second registers P1 and P2 of the factors of IC 1802VRZ mind the knife 3, and the inverse product code at the output of the multiplier 3 is denoted by

(P1) (P2) 0)

where Focr is the operator of the truncation operation with rounding up to eight bits of the 16-bit code (P1) (P2).

The load of register 23 and registers P1 and P2 of multiplier 3 is carried out on the positive front of each I24, and the time programs for entering the generator

control signals P7, P19, P20 (F0p P19P20 - operation code), P26 and I27 determine the function of the generator in time so that the following three modes can be distinguished in its operation (Fig. 2):

1. Storage mode at П7 П26 1 with a duration of T1 KM ™, where K1 is 0, 1, 2,

3, ...; Tti is the duration of the period of the frequency of the following clock pulses I27;

2. Loading mode at P7 1, P26 0, duration T2 T ™;

3. Mode of issue of the result at P7 O, P26 1 with duration of TZ KZ T ™, where KZ 1,2,3

The alternation of the operating modes of the generator (i.e., the inter-synchronization of its input signals and codes and the output of the result to the input-output 10) is provided by the microprocessor and the synchronization circuit and the initial installation of the SMB in which this generator is used.

The principles of alternating generator operation modes are as follows: after the loading mode, the result mode or storage mode can follow, in storage mode, the load mode or result mode can follow, and after the result mode, any of the modes can follow (Fig. 2). ).

The generator works as follows.

During T1, P7, P26 1, in the memory of the generator (i.e., in register 23 and registers P1 and P2 of IC 1802VRZ of multiplier 3) there is information due to the history of its operation, the code output of switch 18 is in the third state at P701, switch 17 generates code F17 FZO when P26 1, and on the address code input 8 (address bus) and code input-output 10 (data bus) codes are formed in accordance with the programs of operation of MW.

During T2 P7 1, P2b 0, the code output of the switch 18 is in the third state, the signals of the code Fop P19P20 are set on the negative edge of the signal P26 0, at inputs 19 and 20, the element 11 generates a signal P11 P19 P20, with P11 1 at input 8 it is set the code F8 of the address of the assignment of a constant, and when P11 0 input-output 10 sets the code F10 of the argument of the trigonometric function (sine at P19 O, P20 0, cosine at P19 O, P20 0, arctangent at P19 1, P20 0) in accordance with the expression

l

a (/ 2) -Ј (/ 2) -Y o | 2

i -i

l p

Opr 2) 0 | 2; i 1

L l l

Odop I Olr

where bit is the digit (0 or 1) of the 1st bit of the code а for i -1,0,1,2, п;

The code determined by the lower digits of the code a and defining the right reduced angle “Pr (l / 2) IGR;

an odd code defining an additional one to / 2 is the reduced angle, i.e. Olr l / 2;

I - (2 + p) -discharge code of the unit in the modified additional code.

In the T2 cycle, at the end of the transients, element 13 generates a signal P13 P26-P31 0, elements 14 and 15 - signals:

P 14

Oopi P 19 0, P20 0; Yopripp 19 0, P20 1; (4) O at P 19 1;

П 15

S0 «-1 atP 19 0, C0 Ј2-1 + Ob at P 19 0, P20 1 O at P 19 1.

and the adder 2, block 5 and the switches 9 and 17 produce codes:

F2 F5 + O ... OP14 P2F28F29; F5 GM4 F 14 F 9 P 11 F 28 V P 11 F 8; F 17 f28

(6)

F 10

-14

(4-2 at 019;

where So and Co are the bit digits of the sign bits of the forward sine and cosine codes of the 4Q angle a, respectively;

F10 is the code formed by the lower bits of the F10 code.

With P11 0, the code F2 is the code of the arc tangent argument so that the connection between the code # and the angle a 45. Ф 2 tgp (tgp) yn +

+ ({d / 3) ap F28 + F29.

(l-2 | 4) priP19 1, l.

(2)

is characterized by:

and at P19 0 - the code of the reduced angle is F 2 P 14 “pr v P 14 Odop Y

 Oops + Oops, (8)

when it overflows, the signal P2 1 is generated, and at P2 0 Oup F28, F29 (the indices yn and an indicate the control and approximating parts of the argument codes tg / J and y, respectively).

During T2, the generator is activated when P11 1 to play the FNF code of the normalizing function, and when P11 0 - to play the trigonometric function

Phf P 19 (P20 sin a v vn 20 cosa) vn 19 arctg / 3 ..

Code calculation (9) is carried out by the method of piecewise linear approximation so that at P19 0 the approximation is performed by the sine function at an angle from 0 to / 2 radians, and at P19 1 by the function of the arc tangent in the range of the argument from 0 to 1, moreover, in each case the number of approximation participants is equal to 2, the value of each segment is equal to

L (P 19 19) 2

-7

(YU)

and the corner point is selected at the beginning of each section of the approximation. Therefore, at the end of the transition process, at the inputs of the multiplier 3, the code of the approximating part of the argument is generated (at A11 0).

(eleven)

F29 P 19 19 (tgjS) an

and function increment code at the approximation site

F 16 P 19 sin woop + A) - sin woop

l

vni9 - () yn- (tg / 3) yn,

(12)

P

where (tg ft) yn f 28 + 2 is the value of the argument at the end of the portion of the approximation of the arc tangent.

At the end of the transients, I27 comes to the generator and I24 P26 vi / 127 0 is formed, on the positive front of which the F1 code F29 codes are entered into the P1 and P2 registers of the multiplier 3, and the F9 code and the signals P11, P15 and P2 are recorded in register 23 (for P2 1

the calculation of the sine code for y / 2 is noted. At this time, the loading mode ends and the dispensing mode begins.

During the TZ, the FZD code and signals are formed at the outputs of the register 23 through the delay time Taz 30 of the register 30 and in accordance with the expressions:

GFZOTZ F9t2; 1n31tz P11t2; ) P32tz P15t2; (PZZtz P2-G2,

(13)

20

where in the right-hand parts are the code F9 and the signals 15 P11, P15 and P2 with the index T2. i.e. formed in boot mode.

Using signals and code element 13 generates a signal A13 P31, block 25 - code

Ф25 ПЗЗ ФЗ ПЗЗ (1 ... 1), (14)

five

0

0

five

0

block 4 with A13 0 is the code of the value of the trigonometric function in the approximation node, adder 1 with A13 0 is the code of the module of the trigonometric function (the sign of this function is determined by the signal P32 produced by the TZ on the signal (5) of period T2), and with A13 1 the blocks 4 and 16 produce the Fnf code of the normalizing function,

At P13 0 and PZZ 1, adder 1 generates an F1 code corresponding to the sine of the angle / 2

In TZ at the end of the transition process-. 5 owls to the generator receives the regular AND 27. by which {i.e. on П27 v П7 0) the result of the operation of the generator

Ф10 Ф18 П13-ФтфИПЗ-Ффф, (15) issued (at П7 0) by the switch 18 to the input-output 10, can be loaded into the memory of any MW device. Further, the generator operation in time is also determined by the MWW operation program.

Claims (1)

Invention Formula A digital function generator containing two adders, a multiplier, - a memory block, a block of EXCLUSIVE OR elements, a NOT element, a first switch, an AND element, the transfer input of the first adder and the input of the first term of the second adder connected to the input of the logical zero of the generator, the second term of the input which is connected to the output of the YSK-5 BOTTOM OR element block, the first information input of the first switch is connected to the input address of the generator constant setting, characterized in that, in order to increase speed, it are given four AND elements, a memory block, two switches, two EXCLUSIVE OR elements. register, element OR, and the clock input of the generator is connected to the first input of the element OR, the output of which is connected to the synchronization inputs of the register and multiplier, the input of the first digit of the operation code of the generator is connected to the input of the element NOT, the first input of the first element AND the input of the first and first inputs of the second switch, the input of the second digit of the operation code of the generator is connected to the first inputs of the second element AND, the first element EXCLUSIVE OR, and the second input of the first element AND, the outputs of the higher bits The second adder is connected to the low bits of the second input of the first and low bits of the first input of the second switch, the first control input of the generator is connected to the select input of the third switch, the output of which is connected to the information input / output of the generator, the first and second high bits of which are connected to the first input of the second element EXCLUSIVE OR, and to the second inputs of the second element AND and the first element EXCLUSIVE OR, respectively, the lower bits of the information input-output of the generator are connected to the bit input of the block EXCLUSIVE OR, the second control input of the generator is connected to the control input of the second switch, the second input of the OR element and the first input of the third AND element whose output is connected to the higher bits of the address inputs of the first and second memory blocks, the outputs of the first and second elements EXCLUSIVE OR are connected to the first inputs of the fourth and the five elements AND respectively, the second inputs of which are connected to the output of the NOT element, the output of the fourth element AND are connected to the transfer input of the second adder and the control inputs of the block of elements EXCLUSIVE OR, the output of the first switch is connected to the information input of the register, the output of which is connected to the second input of the second the register and the lower bits of the input address of the first memory block, the output of the first element I is connected to the control input of the first switch and through the register to the second input of the third element I and the control present input the third switch, the output of the second switch is connected to the lower bits of the address input of the second memory block, the output of the first memory block is connected to the first input of the third switch and the input of the first the summand of the first adder, the output of the second memory block is connected to the input of the first multiplier multiplier and to the corresponding bits of the first input of the third switch, the output of the first element And through the register is connected to two high bits of the second input of the third switch, the lower bits of which are connected to the output the first adder, the overflow output of the second adder through the register is connected to the higher bits of the input of the second term of the first adder and to the control input of the OR block whose output is connected to the younger bits of the second term of the first adder, the input of the block of elements OR are connected to the output of the multiplier, the input of the second factor to the output of the lower bits of the second adder, the output of the second element AND to the second input of the second element EXCLUSIVE OR. FIG. 2