SU1388853A1 - Fixed-point number divider - Google Patents

Abstract

The invention relates to digital computing and can be used in specialized information processing systems. The purpose of the invention is to improve the accuracy of calculations. The goal is achieved by the fact that the device for dividing fixed-point numbers, containing adder 1, blocks 2, 3 elements AND, elements AND 4, 5, 6, counter 10, argument and register 18, contains element OR 11 and counter 17 relevant links. 1 il.

Description

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The invention relates to computing technology and may find application in creating integrated digital processing systems for digital information.

The goal of the invention 11 is to improve the accuracy of the calculations.

The drawing shows the scheme of the proposed device for dividing fixed-point numbers.

The device contains an adder 1, blocks 2 and 3 elements AND, elements AND 4-6, clock inputs 7-9 of the device, counter 10 argument, element OR 11 direct input 12 of the device divider, inverse output 13 of the sign bit of the accumulator 1, direct output 14 is the sign bit of the adder 1, inverse output 15 is the sign bit of the counter 10 argument, inverse input 16 of the device divider, counter 17 of the private register 18, input 19 of the divisible device, output 20 of the private device. Input 21 device arguments,; The clock inputs 7-9 of the device receives a sequence of pulses.

The algorithm of operation of the device for obtaining an n-bit quotient is as follows.

Performs g high-order quotient loops. In this case, in each cycle: the unit is calculated from the argument r ;; using the formula x + y, the remainder is calculated; according to the formula

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Zj. + With X oo,

the values of the higher bits of the quotient are formed and, if the resulting residue X is less than zero, then it is restored by the formula X x + y.

The nth cycles of determining the lower bits of the quotient are completed.

The device works as follows.

To implement the division, the dividend x leads to adder 1, the divider y to inputs 12 and I6 the divisor, the argument (-g) of the scale factor presented in the additional code, to counter 10 of the argument. Let it be necessary to implement an example

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0,0110

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in this case, the input 12 of the divider will contain the code 0,0110, in the adder - I - 0,1010, in the counter of the argument -1,101.

To determine () the quotient of the quotient, 4 division cycles are performed. For () the first cycles, the device operates as follows.

In the first cycle (clock input 7) of each cycle, the divider is subtracted from the code on adder 1 and the unit is added to the contents of argument counter 10. In the second cycle (clock input 8), if on the adder 1 the remainder is positive, then on the leading edge of the s-clock signal 8 to the counting input of the counter 17, one is received. In addition, the trailing edge of the signal from the clock input 8 records the contents of the counter 17 on the register 18, and, if the remainder is negative on the adder 1, it is restored (a divider is added to the remainder).

In the third cycle for r the first cycles in the device, arithmetic and logical actions are not performed.

For subsequent cycles in the first and second cycle, the device operates as described. On the third clock cycle at the input of AND 6, a signal arises, on the leading edge of which a shift is made by one bit to the left of the contents of the adder I and register 18, and on the falling edge of this signal, the contents of register 18 are overwritten on counter 17.

For our example, the formation of the particular on the output register 18, depending on the contents of the adder 1, the counter 10 argument and the counter 17, is as follows.

In the first cycle of dividing by signal. (clock input 7) the inverted value of the divider from input 16 (1.1001) is added to the contents of adder 1 (0.1010). On the adder 1 forms with the code 0,0100. On the leading edge of the signal (clock input B), at the output of the first element I 4, a single signal arises, which receives a single signal at the counting input of counter I7. On counter 17, the code 0001 is generated, which is

the signal front (clock input 8) is rewritten to register 18.

In the second cycle of dividing the signal (clock input 7), negative code 1.1101 is generated on adder 1 and code 1111 is generated on counter 10 of the argument. On the leading edge of the signal (clock input 8), the remainder x1.1101 is restored and on adder 1 code 0,0100.

In the third division cycle according to the signal (clock input 7) on adder 1 (a negative code of 1.1101 is formed, and the counter 10 of the argument is code 0000. On the leading edge of the signal (clock input 8), the rest of X is restored and on adder 1 a code 0 is formed , 0100. On the leading edge of the signal (clock input 9), the contents of adder 1 and register 18 are shifted one bit to the left. On accumulator 1, a code of 0.1000 is generated, and on register 18, a code of 0.0010, On the trailing edge of this signal - the contents of register 18 are rewritten to counter 17,

In the fourth division cycle according to the signal (clock input 7), code 0.0010 is generated on the adder I. On the leading edge of the signal (clock input 8) at the output of the first element And 4, a signal is generated, which receives a single signal at the counting input of counter I7. On counter 17, code 0011 is formed, which is rewritten to register 18 on the falling edge. On the leading edge of the third signal (clock input 9), the contents of register 18 are shifted one bit to the left.

After the end of the fourth cycle, the register 18 will generate the code 00110, which after adding the sign bit (the formation of the sign bit is not considered) will look like 0.00110 ,.

The mean-division error by the algorithm of the proposed device can be determined by the formula

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Claims (1)

Invention Formula A device for dividing fixed-comma-containing numbers containing an adder, two blocks of elements Pi, three elements AND, an argument counter and a register, the input of the divisible device being connected to the setting input of the adder, the left-shift resolution input of which is connected to the left-shift enable input, the output which is the output of a private device, the argument input of which is connected to the installation input of the argument counter, the direct and inverse inputs of the device divider are connected respectively to the first inputs of the first and second And blocks whose outputs are connected respectively to the inputs of the first and second adders of the adder, the inverse and direct outputs of the sign bit of which are connected respectively to the first inputs of the first and second And elements, the first clock input of the device is connected to the second input of the second block of And elements, the second clock input of the device is connected to the second inputs of the first and second elements And, the output of the second element And is connected to the second input of the first block of elements And, the inverse output of the sign bit of the counter a The module is connected to the first input of the third element, And, the second input of which is connected to the third clock input of the device, characterized in that, in order to improve the accuracy of calculations, it contains a private counter and an OR element, and the first clock input of the device is connected to the counting input of the argument counter and with the first input of the 1ShI element, the output of which is connected to the input of the add resolution of the adder, the input of the left-shift resolution of which is connected to the output of the third element I, and with the input of the resolution of the record of the quotient counter, sec th clock input device is connected to the second input of the OR gate and to the input of the register write enable, at Exit of which is connected to data input private counter whose output is connected to data input register, an output of first AND gate is connected to the counting input private counter. 12 16 one