SU1718215A1 - Device to perform vector-scalar operations over real numbers - Google Patents

Abstract

The invention relates to computing and can be used in universal and specialized computer systems for the hardware implementation of the parallel division or multiplication of the numbers represented in the direct code in the form of a fixed comma. The purpose of the invention is to expand the functionality of the device by performing a multiplication operation. The goal is achieved by the introduction of an auxiliary operation unit into the device containing L + 1 operational blocks (L is the number of elements of the vector operand) and the control unit. 2 h. the item of f-ly, 4 silt,

Description

The invention relates to computing and can be used in universal and specialized computer systems for the hardware implementation of vector-scalar multiplication and division of numbers represented in a direct code in the form of a fixed comma. Components X | vector X (U 1,

2L}) and the scalar Y are (n + 1) -bit binary numbers represented in the forward code. In the higher (zero) bit, the sign of a number is fixed, in bits from the first to the nth - the modulus of the number. , 1Hfe {1.2, ..., L}: iyU 1/2. A device for performing multiplication and division operations is known, comprising a receive and output unit, a register, a summation unit, a multiplexer, a control unit, an activity characteristic generating unit, a cycle counter , decoder, switch, elements 2I-OR. And, or

NON EXCLUSIVE OR and trigger with appropriate links 1.

The disadvantages of the known device are low speed and limited functionality, providing simultaneous processing of only two operands.

The closest in technical essence to the present invention is a device for parallel division of numbers, containing L + 1 operational blocks (L is the number of components of the vector operand), a character trigger, a control unit 2.

The disadvantages of this device are the limited functionality that allows only vector-scalar division operations to be performed.

The purpose of the invention is to expand the functionality by executing

go ate

nor the operation of the vector-scalar multiplication of L multiplicable by one factor.

The goal is achieved by the fact that the device for performing vector-scalar operations on real numbers, with holding L + 1 operational blocks (L is the number of components of the vector operand) and the control unit, the input of the 1st

component of the vector operand (1e {1, 2

L}) is connected to the first information input of the 1st operation unit, the first and second outputs of which are connected respectively to the outputs of the i-ro component of the result vector and the 1st sign of the device overflow, the start input and the clock input of which are connected respectively to the start input and the clock input of the control unit, the first output of which is connected to the output of the sign of the end of the operation of the device and the input of the permission of the account of each operational block, the input of the permission of the record of each operational block is connected to the second output a control unit, the third output of which is connected to the output of the device dividing sign of the device, the second information input of each operational block is connected to the fourth output of the control unit, an auxiliary operation block is entered, the count resolution input of which is connected to the first output of the control block, the intermediate code input of which connected to the output of the auxiliary operation unit, the first information input of which is connected to the fifth output of the control unit, the second output of which is connected to the input and recording the auxiliary operation unit, the second information input of which is connected to the fourth output of the () -th operation unit, the inputs of the multiplier divider and the operation code of the device are connected respectively to the inputs of the multiplier divider and the operation code of the control unit, the sixth output of which is connected to the sign forming input The 1st operational block, the input of the sign of multiplying by zero of which is connected to the seventh output of the control unit, the eighth output of which is connected to the first information input (L + 1) -ro of the operational block Single inputs characteristic multiplying by zero, mark and forming a clock input of which is connected with the input logical O device, the start input of which is connected to a clock input of the 1st operation unit, the third output coupled to an output of the 1st mark devices result vector component.

The goal is also achieved by the fact that the operational block contains the UNEMATICAL element, multiplexer, sign trigger, register, AND element, shifter and adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected multiplying by zero of which is connected to the first input of the element I, the second input of which is connected to the output of the register, the input of the first term of the adder, the information input of the shifter and the second output of the block, The sign forming of which is connected to the first input of the UNEQUALITY element, the second input of which is connected to the input of the first bit of the information input of the block, the input of which the permission of the Account is connected to the control input of the multiplexer, the output of which is connected to the information input of the register whose input of the record is connected to the input enable the recording of a block, the clock input of which is connected to the clock input of the sign trigger, the information input of which is connected to the output of the UNEMINABLE element, and the output from the third output of the first output of which is connected to the output of the AND, and a fourth output - to an input of the second term of the adder and the output shifter, a shift control input of which is connected to the second data input unit.

The goal is also achieved by the fact that the auxiliary operation unit contains a multiplexer, a register and an adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the first information input of the block, the counting input of which is connected to the control input of the multiplexer whose output with the information input of the register, the output of which is connected to the output of the block and the input of the first term of the adder, the input of the second term of which is connected to the second information Discount unit input, write enable input is connected to the input of register entries.

A comparable analysis of the proposed solution with the prototype shows that the proposed device differs from the known set of blocks and the relations between them, resulting in a positive effect, whereby the proposed technical solution meets the criteria of the invention of novelty.

The use of the above set of distinctive features in other objects of similar purpose is unknown, which, in combination with the set of known features, provides the possibility of obtaining a positive effect, whereby the proposed technical solution meets the criteria of the invention are significant differences.

All elements of the claimed device can be performed on commercially available chips, whereby the proposed solution meets the criteria of the invention for the technical solution of the problem.

The operation of the device is based on the use of iterative multiplication and division algorithms that implement a multiplicative method of calculation.

The device implements vector-rock pn operations of multiplying and dividing the numbers represented in the direct code and fixed-point form. The components Xi of the vector operand X (1c {1,2L}), the scalar operand Y, and the components Zi of the vector result Z are binary (n + 1) -bit binary numbers represented in the forward code. In the higher (zero) bit, the sign of a number is fixed, in bits from the first to the nth - the modulus of the number.

utie tfCiiadeLo vfc4U, ..., tf, .M:

The type of operation to be performed is determined by the operation code d & {0,1}. When the mouth is 7X |

Roystvo makes calculations Zi -y-,

when calculating -YVit {1,2L}.

Both operations are performed using recurrence relations.

, U

., - 2 lK. , a2l.,.

ak-oi.letc

about,., b.,; .,. ,,., -,

where k is the number of iterations being performed, and {1,2, ..., t} is the number of iterations necessary to obtain the results of the operation. 45

The value of jk when executing the kth iteration is chosen to be equal to the number of the highest zero bit of the code Ck-1.

In the case of the multiplication operation, the initial values of the variables are determined by the ratios

Vk {1,2L} aio Xi; bo 1/2; Co 1/2 +

+ (1-TO (2)

in the case of a division operation,

VU {1,2L} aio Xi; bo Y; Co Y (3) 55

Calculations continue until the condition of the next tth iteration is satisfied

1 m; 1-Ct-, 2

five

10 15

20 25 30

35

40

45

ate

55

where m is the multiplicative resolution of the calculations, which provides the result with a given accuracy (m n).

The resulting values are calculated depending on the type of operation being performed, either the product or the particular.

The final calculation result for each operand is given in the form of (n + 1) - a bit code, in which the most significant (zero) bit is significant, and the bits from the first to the n - th digit numbers of the result.

FIG. 1 shows a block diagram of the device; in fig. 2 - structural diagram of the main operating unit; in fig. 3 is a block diagram of the auxiliary operation unit; in fig. 4- functional block diagram of the control unit.

The device contains L + 1 main operational blocks 1, auxiliary operational block 2, control block 3, has input 4 for entering a multiplier or divider, input 5 of the operation code, start input 6, clock input 7, input 8 of logical O, L information inputs 9 , the output 10 of the sign of the end of the operation, the output 11 of the characteristic of dividing by zero, L outputs 12 bits of the result overflow, L outputs 13 results, L outputs 14 characters of the result.

The main operational unit (Fig. 2) contains a multiplexer 15, a register 16, an adder 17, a shifter 18, the UNEQUALITY element 19, a valve node 20, a character trigger 21, has first 22, second 23, third 9, fourth 24, fifth 5, the sixth 26 and seventh 27 inputs, the first 12, the second 13, the third 14 and the fourth 28 outputs.

Auxiliary operational unit (Fig. 3) contains a multiplexer 29, a register 30, an adder 31, has first 32, second 33, third 34 and fourth 35 inputs and output 36.

The control unit (Fig. 4) contains n + 1 elements AND 37, n-1 elements HE 38, 2 n - 2 elements AND 39, n-1 elements OR 40, trigger 41, ch-1 elements AND 42, element And 43, element OR 44, element OR 45, element AND 46, element OR 47, two elements M 48, has the first 4, second 5, third 6, fourth 7 and fifth fifth 49 inputs, first 50, second 51, third 52, fourth 10 , fifth 53, sixth 54, seventh 11 and eighth 55 exits.

The device works as follows.

In the initial state, V lЈ {1,2L} on

input 9. I device and then to the third input of the operation unit 1.1 enters the value of the 1st operand Xi. To the input 4 of the device and further to the first input of the control unit 3

the value of the operand Y is received. The clock pulses (TI) are continuously received at the input 7 of the device. The END OPERATION feature, coming from the fourth output of the control unit 3 to the fourth inputs of the 1 | .VIe {1,2, ..., L + 1} units, the second input of the unit 2 and to the output 10 of the device, has a single value. The operand codes supplied to the third inputs of the main operating units 1.IVk {1,2, ...,} are converted from (n + 1) - 10 bits to (n + 2) -bit format () by inserting the bits yes overflow d for the purpose of revealing situations, code SpI

2.1, as well as additions (V-n) of lower numeric bits, which are assigned the null- 15 left value. The change in the numerical part of the operands is carried out in order to ensure the permissible error of computation arising due to the truncation of numbers shifted beyond the limits of the discharge grid.

The code of the operand Y is fed to the first input 4 of the device and then to the first input of the control unit 3. Depending on the operation code d, arriving at the second input 5 of the device and further to the second input of the control unit 3 25, in the control unit the initial values of the variables bo and Co are formed according to expression (2) for and expression (3) for coming from the second output control unit to the first input 30 of the auxiliary operation unit 2 and from the third output of the control unit to the third input of the main operation unit 1.L + 1. The generated initial values of the variables bo and Co are complemented with zero - 35 to V numeric bits.

At the input 8 of the device and further to the first, second and sixth inputs of the main operation unit 1.L + 1, a logical signal O.40 is applied.

To start the calculations synchronously with one of the TIs, the Start signal is sent to the input 6 of the device. The Start signal at the fifth output of the control unit 3 generates a Signal signal that enters the 45th inputs of the main operating units 1 and the third input of the auxiliary operation unit 2, ensuring that the operands arriving at the third inputs of the main operating units 1.IVI & 50

{1,2l + 1} and first auxiliary input

operational unit 2. At the same time, the Start signal goes to the sixth inputs of the main operational units 1.1UC1.2L},

ensuring that the triggers remember the sign of these blocks of formed characters of the Zi results. From the third output of the main operation unit 1.L + 1, the V-bit information code is fed to the fourth input of the auxiliary operation unit 2.

From the output of the auxiliary operation block 2t, the higher bits of the LM code (code bk-i) are fed to the fifth input of the control block 3. If all bits of a bk-faun are one or the most significant bit of a code is zero, the END OF OPERATION feature retains a single value and no calculations are performed. At the same time on the second

the outputs of the 1.IVIe {1,2L} blocks are formed

results depending on the operation code and the sign of the end of the operation. In the case of the multiplication operation () and the zero value of the operand Y, the zero output is formed at the second outputs of the blocks 1.1. When performing the division operation () and the zero value of the operand Y on the second output of block 1, IVk {1,2, .., L}, the value is not determined, at the same time there are signs at the outputs 11 and 10 of the device, respectively, DIVIDING IN ZERO AND SCREEN OPERATIONS . In case all bits of the code received at the fifth input of control unit 3 are equal to one, at the second output of operating unit 1.IV &

C, 2, .., L} regardless of the operation code, the result Zi is generated, which is represented in the forward code.

If there is an m-bit code bVi on the fifth input of control unit 3 that contains one unit and at least one zero in the high order, the END OF OPERATION sign at the fourth output of control unit 3 takes a zero value and an iterative process is performed in the device calculations in accordance with expressions (1).

Next k-iteration V ke {1,2t}

is implemented in the device as follows. At the eighth output of the control unit 3, an m-bit unitary code Ik is generated, containing a single value in the jkth bit and zero values in the remaining bits, which is fed to the sixth input of the operation unit 1.1U1e {1,2, .. ,, The operation units 1 and the auxiliary operation unit 2 are formed in accordance with expressions (4) of the value ai.Vie

{1,2L}, bk and Ck respectively. With the arrival of the next TI, at the fifth output of the control unit 3, the Signal signal is formed, according to which the generated values aikV le {1,2, ..., L}, bk and ck are entered into the registers of the operational blocks 1 and 2, respectively. Thereafter, the values of aik, bk and Ck are formed at the second outputs of the main operating units 1 and the auxiliary operating unit 2, respectively.

This completes the next iteration.

The iteration process continues until then; until, as a result of the implementation of the next tth iteration, all m bits of the bk-1 code received at the fifth input of control unit 3 will not be equal to one at the same time. At the same time, the control unit stops generating signals. The entry is on its fifth input and forms a single value of the END OPERATION feature at the fourth output of the block.

At the end of the calculations, at the second output of block 1.No. {1.2L}, the result module Zi is formed at the third output, the result sign, at the first output, the value of the overflow bit.

The main operating unit operates as follows.

In the initial state, the first 22, second 23, third 9, fourth 24, fifth 25, sixth 26 and seventh 27 blocks of the block receive the values of the attribute MULTIPLICATION ON

ZERO, operand sign Y, YoЈ {a 0VM1.2L}.

bo}, sign END OPERATION, signal Entry, Start signal, unitary code 3k, respectively.

The unit value of the END OPERATION feature coming from the input 24 to the multiplexer control input / ensures that the code | o passes from the second information input of the multiplexer to its output and further to the information input of the register 16. As a result, with a single value of the END OPERATION signal the Entry ensures recording o value in register. During the kth iteration V ke {1,2 .., ..:}, the value Јk-i eVCe {1,2L} bk-l} from the output of register 16 is fed to the first input of the adder 17, as well as to the first input of the shifter 18. On the second. Input of the shifter from the input 27 of the block comes the unitary code 3. The shifter 18 shifts the information received at the first information input to the right (towards the lower bits) by the number of bits equal to the number of a single bit in the unitary code received at the second control input, with the zero bits replaced. As a result, at the output of the shifter 18, a code Ј k-1, 2- is generated, which is fed to the second input of the adder 17. as well as to the fourth output 28 of the block. At the output of the adder 17, the value Ј k {aikVU {1.2,.,., L} bk} is formed in accordance with expressions (1). arriving at the first information input of the multiplexer 15. The zero value of the sign END OF THE OPERATION ensures the passage of the code

0

 the output of the multiplexer 15 and further to the information input of the register 16.

Simultaneously with the submission to the third information input 9 of the 1st block Vte {1.2C

the values of to the second input 23 are signed by the operand Y, which is then fed to the first input of the element UNEQUAL 19. The second input of this element is given the value of bit Јо (0), which is the sign of the operand X |. The sign of the result formed in the UNEQUALITY i9 element comes from its output to

trigger input

ABOUT

result mark which

five

0

five

0

five

0

five

0

five

according to the Start signal, which arrives at the second input, it synchronizes the memorization of the sign of the result before starting a new operation.

The value of the result module is formed depending on the attribute MULTIPLICATION TO ZERO entering the first input 22 of the block and further to the first inverse input of the valve node 20. In the case of a single value of this characteristic, a zero result is generated at the output of the valve node and then at the second output of the block.

The fourth output 28 of the block is designed to issue a shifted code Ј s. for the purpose of using it by other operating units.

Auxiliary operating unit 2 operates as follows. The first 32, second 33, third 34 and fourth 35 inputs receive the value Ј Ј Ј {Co}, the sign END OF OPERATION, the value of the Signal signal and the value with k 1.2J {). A single value of the END sign, coming from the input 33 to the control input of the multiplexer 29, ensures that the second information input of the multiplexer 29 passes the soco code to the output and then to the information input of the register 30. During the k-th iteration, the {&1.2; 1.2} value Јir- iЈ {Ci -i} c register output 30 is fed to the first input of the adder 3 t, the second input of which receives the value from the fourth input 35, which is the value bk-i.2 J At the output, the output point 31 is formed in accordance with the expressions ( 1) Јkf {Ck} value, incoming e on the first information input multipleksor- 2r. The oval value of the END OPERATION feature ensures the passage of the code Ј i / to the output of the multiplexer 29 and then to the information input of the register 30.

The control unit is provided as follows. At first 4. YUOP.-H-. 5. the third 6. the fourth 7 and the fifth 49: vv, .n.;. I p.chock receive (gi 1) -size 1 operand Y in the direct code, the code of the op. -S-p. -And g signals

Start, TI, m senior bits of the Sy code (Sy code), respectively,

From the first to (t-1) -th elements And 42, they form a unitary (t-1) -radiating code 3k, having a single value in the bit, whose number is equal to the number of the highest zero bit of the Sy code, and zero values in the remaining bits dah, which enters the eighth output of the 55 block.

When the unit of all bits of the code is equal at the fifth input 49 of the block at the output of the element And 43, a single signal level is formed, which is fed to the first input of the IL-44 element. At the second input of this element is the inverted value of the first code bit generated by the OR element 45 If the operand is equal to zero, the Y output of this element will be a single value. Thus, at the output of the element OR 44, the sign END OF OPERATION is formed, which is fed to the fourth output 10 of the block and to the inverse input of the element 46, prohibiting TI from the fourth input 7 of the block to the output of this element. At the output of the element OR 47, which is simultaneously the fifth output 53 of the block, when a signal is received. Start at the third input 6 or when the TI arrives at the fourth input 7 of the block and at zero sign. END OPERATION At the output of the element OR 47, the Entry signal is generated. The first input of the 4th block is supplied with the (n + 1) -alloy code of the operand Y, which is bitwise supplied to the first inputs from the first to (n + 1) -th elements of AND 37. The first element of And 37 passes the output 50 to the output 50 the sign of the operand Y. At the second inputs of the elements AND

37 A start signal is received. The group of elements And 37 from the second to (n + 1) -th, elements NOT

38c of the first through (p-1) -th and AND 39 elements of the first through (p-1) -th ensures the formation of loading constants coming from the outputs 51 and 52 of the control unit as initial values into the operating units 1.L + 1 and 2. and generated depending on the operation code d, arriving at the second input 5 of the control unit and memorized on the trigger 41 by the synchronization signal Start. In the case of the multiplication operation on the outputs 51 and 52

block values are formed

in the case of division, lYt and 1YI, respectively. The value of the signal generated at the output of the first element AND 48 is fed to the sixth output 54 of the block as a sign value of the MULTIPLE ZERO. Formed at the output of the second element And 48 the signal value is supplied to the seventh output 11 of the block as the value of the characteristic. DIVISION BY ZERO.

Thus, the positive effect of the proposed device is to 5 extend the functionality,

Claim 1. An apparatus for performing vector-scalar operations on real numbers, containing L + 1 operational blocks (L is the number of components of the vector operand) and a control unit, the input of the 1st component of the vector operand (AND {1, 2L}) connected to

5 with the first information input of the 1st operation unit, the first and second outputs of which are connected by the outputs of the 1st component of the result vector and the 1st sign of the device overflow,

0 the start input and the clock input of which are connected respectively to the start input and the clock input of the control unit, the first output of which is connected to the output of the sign of the end of the operation of the device and the input 5 of the account resolution resolution of each operational block, the write enable input of each operational block is connected to the second output of the control block, the third output of which is connected to the output of the indication of the character of the device to zero, the second information input of each operation unit is connected to the fourth output of the control unit, characterized by Due to the fact that, in order to expand the functional possibilities due to the multiplication operation, an auxiliary operation block was inserted into it, the counting permission input of which is connected to the first output of the control unit, the intermediate code input of which is connected to the output of the auxiliary operation block, the first information input which is connected to the fifth output of the control unit, the second output of which is connected to the input of the recording permission of the auxiliary operation block, the second information input of which is connected with the fourth output (L-1) -ro of the operational block, the inputs of the multiplier divider and the operation code of the device are connected respectively to the inputs of the multiplier divider and the operation code of the control unit, the sixth output of which is connected to the input of the formation of the sign of the 1st operating unit block, sign input

5 multiplied by zero is connected to the seventh output of the control unit, the eighth output of which is connected to the first information input (L-M) -ro of the operation unit, the inputs of the sign of multiplying by zero, forming a sign and

the clock input of which is connected to the input of a logical device O, the start input of which is connected to the clock input of the 1st operation unit, the third output of which is connected to the output of the sign of the 1st component of the result vector of the device.

2. The device according to claim. With the fact that the operating unit contains the UNCHARACTER element, multiplexer, character trigger, register, AND element, shifter and adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the first information the input of the block, the input of the sign of multiplying by zero of which is connected to the first input of the element I, the second input of which is connected to the output of the register, the input of the first term of the adder, the information input of the shifter and the second output Lok, which form a sign input coupled to the first input element unequal; the second input of which is connected to the input of the sign bit of the first information input of the block, the input of the account resolution of which is connected to the control input of the multiplexer, the output of which is connected to the information input of the register, the recording input of which is connected to the input of the resolution of recording of the block a sign trigger whose information input is connected to the output

of the UNEQUALITY element, and the output is with the third output of the block, the first output of which is connected to the output of the element I, and the fourth output to the input of the second term of the adder and the output of the shifter, the input

the shift control of which is connected to the second information input of the block.

3. The device according to claim 1, that is, with the fact that the auxiliary operational block contains a multiplexer, register and

an adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the first information input of the block, an input of the account resolution

which is connected to the control input of the multiplexer, the output of which is connected to the information input of the register, the output of which is connected to the output of the block and the input of the first term of the adder, the input

The second addend of which is connected to the second information input of the block, the write enable input of which is connected to the register entry input.

Fig.Z

Claims (3)

Claim 1. A device for performing vector-scalar operations on real numbers, containing L + 1 operating units (L is the number of components of the vector operand) and a control unit, and the input of the Ι-th component of the vector operand (to {1,2 ..... ! _}) is connected to the first information input of the Ι-th operational unit, the first and second outputs of which are connected corresponding to the outputs of the 1st component of the result vector and the! -th sign of overflow of the device, the trigger input and clock input of which are connected respectively to the trigger and clock input m the input of the control unit, the first output of which is connected to the output of the sign of the end of the operation of the device and the input of the account resolution of each operating unit, the write enable input of each operation unit is connected to the second output of the control unit, the third output of which is connected to the output of the sign of division by zero of the device, the second information the input of each operating unit is connected to the fourth output of the control unit, characterized in that, in order to expand the functionality by performing the operation more ii, an auxiliary operating unit is introduced into it, the account resolution input of which is connected to the first output of the control unit, the intermediate code input of which is connected to the output of the auxiliary operating unit, the first information input of which is connected to the fifth output of the control unit, the second output of which is connected to the recording permission input auxiliary operating unit, the second information input of which is connected to the fourth output (L-1) -ro of the operating unit, inputs of the divisor multiplier and device operation code connected respectively to the inputs of the divisor multiplier and operation code of the control unit, the sixth output of which is connected to the input of the l-ro sign of the operating unit, the input of the multiplication by zero sign is connected to the * seventh output of the control unit, the eighth output of which is connected to the first information input ( 1_ + 1) -th operational block, inputs of the sign of multiplication by zero, the formation of the sign and <the clock input of which is connected to the input of the logical O device, the start input of which is connected to the clock input of the Ι-th operational a block, a third output coupled to an output sign Ι-th vector component of the result of the device. 2. The device according to p. 1 ,. It is inconsequential * that the operating unit contains an element of DISPARABILITY, a multiplexer, a sign trigger, a register, an AND element, a shifter and an adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the first information input of the block, the sign input multiplying by zero which is connected to the first input of the element And, the second input of which is connected to the output of the register, the input of the first term of the adder, the information input of the shifter and the second output of the block, the input of the Nia mark which is connected to the first input element unequal; the second input of which is connected to the sign digit input of the first information input of the block, the account resolution input of which is connected to the control input of the multiplexer, the output of which is connected to the information input of the register, the recording input of which is connected to the recording permission of the block, the clock input of which is connected to the clock input a sign trigger, the information input of which is connected to the output 5 of the element DISABILITY, and the output with the third output of the block, the first output of which is connected to the output of the element And, and the fourth output with the input of the second term of the adder and the output of the shifter, the input 10 of the shift control of which is connected to the second information input of the block. 3. The device pop. 1, in that the auxiliary operating unit comprises a multiplexer, a register and 15 an adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the first information input of the unit, the account resolution input 20 of which is connected with the control input of the multiplexer, the output of which is connected to the information input of the register, the output of which is connected to the output of the block and the input of the first term of the adder, the input 25 of the second term of which is connected to the second information the input of the block whose recording permission input is connected to the register write input. Fig