SU1265763A1 - Dividing device - Google Patents

Abstract

This invention relates to the field of computing. The purpose of the invention is to expand the scope of application by allowing the processing of numbers represented by an additional code. The device contains the registers of the dividend and the divider, the rounding adder, the multiplier. the digit encoder of the quotient, the quotient forming unit, containing the adder-subtractor and register, the control unit, the divisor sign trigger, two groups of modulo-two addition elements, the modulo-addition element, and the next remainder formation block, containing the adder-subtractor. The essence of the invention is that for processing operands in the additional code, the higher (k) s of the divisible and divisor bits are inverted in the case of negative operands and are used to form the K parts of the bits and the device circuits are tuned (L depending on the signs of the dividend and divisor. 2 Il.

Description

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The invention relates to computing and. can be applied in the development of high-speed devices of division convenient for manufacturing as part of large integrated circuits.

The aim of the invention is to expand the field of application of the device by allowing the processing of numbers represented by an additional code.

FIG. 1 is a diagram of a device for dividing; FIG. 2 is a control block diagram.

A device for dividing binary numbers (FIG) contains U-bit registers 1 and 2, respectively, of a divisible and a divider, a private formation unit 3, a control unit 4, a trigger 5 for the divisible character (k + 3) of the addition elements 6 modulo two first group (, h is the size of operands), () of modulo-two addition elements 7 of the second group, modulation addition element 8, rounding modifier 9, 10-digit encoder, multiplier 11, and block

12 forming the next balance. Block 3 contains an adder-subtractor

13 and register 14, block 12 - adder 15.

The device has a bus 16, the values of I, the bus 17 for starting the device and the bus 18 are number of strokes.

Block 4 (Fig. 2) contains the generator 19, the counter, 20, the element OR 21 and the element And 22.

The device for dividing works as follows.

In the initial state in the register 1 the h-digit additional code of the dividend is stored, in the register 2 - n

-digit additional divisor code (it is assumed that the dividend and divisor are binary numbers with a sign), in trigger 5 is the sign of the dividend, the divisor sign is in the higher digit of the register 2. Register 14 has been reset in the initial state.

Highs from register 1 output. (K + 3 bits are received for one group of inputs of addition elements 6 modulo two, and the other output group receives the sign bits of the dividend from trigger 5, and the opposite code is formed at the outputs of these addition elements 6 modulo two Ck + S) most significant bits of the dividend, if the dividend is a negative number, or a direct code (k + 3) most significant bits of the dividend, if the dividend is a positive number.

5 The highest bits of the divider from the second to (k + 3) - and from the output of the register 2 are fed to the inputs of the elements 7 of addition modulo two second groups, on which similar 0 transformations occur. Element 8 of modulo two receives the signs of the dividend and divisor from trigger 5 and high register register 2, respectively. On this modulo two element 8, the sign of the obtained quotient is formed (depending on the sign of the dividend and the divisor), which is fed to the control inputs of the adder-subtractor 13 and the adder 20 of the Subtractor 15.

From the outputs of the modulo 7 elements, the two direct code of the higher digits of the divider from the second to (k + 3) -and enters the input of the adder 25 9 rounding, in which the unit divider is added to the (k + 3) bits of younger bit d. This eliminates the possibility of getting a private 30 in excess in the encoder 10. The inputs of the encoder 10 receive (k + 3) most significant bits of the dividend from the output of elements 6 of addition modulo two and (k + 3) bits of the rounded divider from the output of the sum of 35 torus 9, and the most significant bit (k + 3) of the bit code the rounded divider takes the value of the carry from. the older bit of the adder 9. In the encoder 10, a k-bit 40 regular direct code of the private is formed, and a quotient is formed by dividing the truncated divisible by the truncated

divider.

Absolute error (difference

between the value of the quotient obtained by dividing ii-bit numbers and the value of the quotient obtained by dividing the truncated (| c + 3) -digit numbers) is in the limits,

O f: 2

Claims (2)

In this case, the value of 1s-bit private получ, obtained in the encoder 10 digits, private, can be either equal to 55 but the value of the k-bits of the particular, obtained by dividing h-bit numbers, is only one less than the smallest bit with a weight of 2 ( In the following, we will speak, respectively, of the exact and inaccurate values of the k-bit quotient at the output of the encoder 10). The resulting k-bit single quotient from the output of the encoder 10 is fed to the input of the multiplier multiplier 11. To the inputs of the multiplicand multiplier 11 enters And-bit additional code divisible from the output register 2. In the multiplier 11, the product of the n-bit divider by the k-bit quotient is formed, and, if the divider is negative, multiplication is performed in additional codes if the divider is positive, the multiplier multiplies in direct codes. The operation is selected by a sign bit of the h-digit divider code. The product formed in multiplier 11 is fed to adder-subtractor 15, with which the next balance is formed, which is defined as the difference (sum) of the contents of register 1 and the product obtained in multiplier 11, if the quotient is positive (negative). The sign of a private is formed modulo two on the element 8. Thus, in each operation cycle of the device for dividing binary numbers, a remainder and a k-bit quotient are formed. The remainder received at the output of adder-subtractor 15, shifted by (k-1) bits to the left (towards the higher bits) is fed to the information inputs of register 1. On the falling edge of the pulse from block 4, the remainder is entered into register 1 and serves as the next operation of the device as a dividend. The k-bit quotient from the output of the encoder 10 also goes into the totalizer subtractor 13, in which the quotient generated by this clock is corrected. The correction of the quotient is made by adding (subtracting) to (h-k + 1) the younger discharge of the quotient obtained for a given tick, 1-bit quotient obtained at the current tic (and its corrective is a hundred). if the quotient is positive (negative). On the falling edge of the pulse from block 4, the corrected quotient is written to 634 register-14. Thus, for (h-1) / / (k-1) device operation cycles in register 14, an rt-bit quotient is formed in an additional code. Since the private obtained in this way may not be accurate, it may be necessary to correct the resulting private and residual. For this, it is necessary to subtract (add) the divider from the remainder obtained in register 1, if the resulting h is the bit quotient positive (negative). If, as a result of performing this operation, transfer occurs from the higher bit (modulo the remainder is less than the divisor), then the resulting quotient and the remainder are exact. If no transfer occurs (modulo the remainder is greater than the divisor), then the quotient and the remainder are inaccurate and need to be corrected. In this case, it is necessary to add (subtract) a unit to the received h-bit if the partial is positive (negative). The exact value of the remainder is the result of subtracting (adding) the contents of registers 1 and register 2 if the quotient is positive (negative). In block 4 of the control, in the initial state, the counter 20 is reset. When a start signal is received via bus 17, counter 20 records at .4 the number of division cycles. Since the number of division cycles is different from O, the OR element 21 is set to one and the element 22 is thus open. The pulses of the generator 19 begin to flow to the output of block 4, from which they go to the control inputs of the register 1, and 14, As well as to the input of the subtraction of the counter unit 20. On the trailing edge of the pulse in the counter 20, the number of ticks decreases by 1. After the execution of the counter 20 is reset, the FDI element 21 is set to zero and the element 22 is closed. Thus, Lok 4 goes to its original state. The invention The device for dividing, containing registers of a dividend and a divider, a control unit, a rounding adder, an encoder is a private digit, a private generation unit, a multiplier, a next remainder j formation unit whose first group of information inputs is connected to the outputs of the dividend register, and the second group information inputs - with the multiplier outputs, the information inputs of which are connected to the outputs of the encoder of private digits and the register divider, the first group of inputs of the encoder of private digits is connected to the outputs A rounding out dresser whose transfer input is connected to a device value bus 1, the private digit encoder outputs are connected to the information inputs of a private shift control input unit which is connected to the output of the control unit and the control record of the dividend register, whose information inputs are connected to a shift by k time. Rows to the left (P is the width of the operands) with the outputs of the block forming the next residue, characterized in that, in order to expand the scope of application by providing the possibility of processing the numbers represented by the additional code, two of them are introduced into it. modulo two groups of elements, modulo two addition elements and a divisible sign trigger, a private block contains a subtractor and a register, and the next remainder block is a totalizer – subtractor, whose information inputs and outputs are information inputs and outputs of a block of the next balance, and the control input is connected to the control input of the adder-subtractor of the private formation unit and with the output of the modulo two element, the first input of which is connected to the first inputs dami elements modulo two of the first group and the output of the sign of the dividend, and the second input - with the first inputs of the addition elements modulo two of the second group and the output of the first digit of the divider register, the second inputs of the addition elements modulo two of the first group are connected to the outputs from the first the (K + 3) th register of the dividend, and the outputs with the second group of inputs of the encoder of the quotient of the quotient, the second inputs of the modulo two of the second group are connected to the outputs of the bits from the second to (k + 2) th register , and exits -. with entrances r The rounding adder views, in the private formation block, the register outputs are connected to the higher-order information inputs of the adder, the outputs of which are connected to the information inputs of the register, the recording control input of which is connected to the shift control input of the private formation block whose information inputs are connected to the lower ones bits of the adder-subtractor.