SU1397903A1 - Division device - Google Patents

Abstract

The invention relates to computing technology, namely to multiplying-dividing devices of a computer, and can be used to build high-speed specialized computing devices, as well as in the development of fast-acting dividing devices suitable for manufacturing as part of large integrated circuits (LSI). . The aim of the invention is to expand the scope of use due to the possibility of processing both positive and negative normalized numbers. The device contains input registers 1, 2 of the dividend and the divider, block 3 for calculating the reciprocal, intermediate registers 4.5, block 6 multiplication, output register 7, inputs 8, 9 of the dividend and divider, output 10 of the quotient, clock input 11. Block 3 contains a controlled converter 12 to the additional code, nodes 13, 14 of the tabular memory and algebraic sum SL

Description

WITH

x

with

about her

The invention relates to computing, namely to multiplying-dividing devices of a computer, and can be used to build specialized high-speed computing devices, as well as in the development of high-speed dividing devices suitable for manufacturing as part of large integrated circuits (LSI),

The aim of the invention is to expand the scope due to the possibility of processing both positive and negative normalized numbers.

The drawing shows a block diagram of a device for dividing.

The device contains an input register 1 of the dividend, an input register 2 of the divider, block 3 for calculating the reciprocal, first 4 and second 5 intermediate registers, block 6 multiplication, output register 7, input 8 for the divide, input 9 for the divider, output 10 for the private and clock input 11 .

Block 3 contains a controlled converter 12 to the additional code of nodes 13 and 14 of the tabular memory and adder 15 (algebraic).

The information inputs of registers 1 and 2 are respectively the input 8 of the dividend and the input 9 of the device divider. The clock inputs of the registers 1, 2, 4, 5 and 7 are connected to the clock input 11 of the device. The output of the register 1 divisible is connected to the information input of the first intermediate register 4, the output of which is connected to the input of the first multiplier of block 6.

The input register 2 of the divider is connected to the output of the sign bit divider with the control inputs of the converter 12 and the adder 15 and the third address input of the node 13, the output with the information input of the converter 12.

The first and second address inputs of node 14 are connected respectively to the first and second groups of outputs of converter 12, the first and second address inputs of node 13 are connected respectively to the first and third groups of outputs of converter 12. The outputs of nodes 13 and 14 are connected respectively to the first information input (the input is decremented) and the second information input (input of the subtracted) adder 15, the output of which

Q

0 5

about

0 5

five

0

five

connected to the information input of the second intermediate register 5.

The input of the second multiplier unit 6 is connected to the output of the second intermediate register 5, the output to the information input of the output register 7, the output 10 of which is the output of the device.

The input registers 1 and 2 and the output register 7 are designed for short-term storage of operands, respectively, of the dividend, divider and private, as well as for providing, together with intermediate registers 4 and 5, the conveyor data processing method. All the indicated registers have a size corresponding to the charge of operands entering the device.

Converter 12 is designed to convert the fractional part of the divider operand from the additional code to the direct code and can be implemented as a multi-bit combinational circuit. Nodes 13 and 14 are designed to store values that are used in the process of finding the reciprocal of the divider. Node 14 is designed to store reference values, node 13 is an amendment to the reference value of the reciprocal;

The adder 15 is designed to refine the value of the reciprocal of the divider. It can be executed in the form of a multi-bit combinational circuit.

Block 6 is designed to find the product of the dividend by the reciprocal of the divisor and can also be made in the form of a multi-bit combinational circuit that allows multiplication of the numbers represented in the additional code.

The device implements the method of dividing, which consists in the preliminary determination of the reciprocal value C of the divider X and its subsequent multiplication by the divisible Y. In this case, it is assumed that the input operands of the dividend and the divisor are n-bit binary numbers presented in the additional code which code is fixed after one bit of the whole part, and 1 f | X | 2, One of the methods for calculating the C 1 / X function is a piecewise linear approximation method, according to which the range of variation of the argument is divided into intervals, the number of which is determined by the required accuracy. Each of the approximation intervals is divided into subintervals.

In order to be able to process both positive and negative numbers in the device for calculating the function S., are carried out in accordance with the expression Q

tc,: a.n -x, W-c, K

The encoders in the additional code are written to the input registers 1 and 2, respectively. In the converter 12, the fractional part of the divider X is converted to the direct code. At the address indicated by the m most significant bits of the fractional part X, represented in the direct code, from the node 14, the reference value of the reciprocal value C is selected, which goes to the output

Lb

YOP

where X is the value of the argument of the initial (reference) point of the k-th subinterval j, the reference value of the reciprocal of value C -. on the k-th sub-ok

20

Bj

M; one

J

k

terval;

the value of the correction to the inverse of the argument Xj J the value of the tangent of the angle of inclination j-ro of the approximation segment of the function С abscissi

0,1,2, ..., 2п-1 (n is the width of the input operands of the dividend and the divisor, O, 1,2, ..., 2 (1 is the number of 30 in the higher bits in the fractional part of the divider, by which the value of Mi is determined),

0,1,2, ..., 2 (m 1, m is the number of most significant bits of the fractional part of the divider, which determine the value

subtractable adder 15; At the same time, at the address indicated by the 1 most significant and (n - m - 2) best bits of the 15th fractional part X. presented in the direct code, the value B is selected from the node 13, which is fed to the input of the decremented adder 15. The value of B has the sign opposite to the sign of the divider X. In the adder 15, the reciprocal of the divider is calculated, which is the sum of X O, and the difference

i: 4.iiJib v A v rit-T / i fg f rr

1 / X to the axis 25 tB, on - С ,, if X 0. Upon the arrival of the second clock pulse, the value of the reciprocal of the divider is written to intermediate register 5, and the value of Y is recorded simultaneously to intermediate register | 1p 4. Contents of intermediate registers 4 and 5 enters block 6, at the output of which the sought quotient is formed. Upon the arrival of the third clock pulse. The resulting number is written to the output register 7 and is outputted from it to the output 10 of the device.

35

Sd values)

Claims (2)

Invention Formula " this s „ 1 / IX „1, sign  Ok h ok occurs in the case of positive, minus sign - negative values of the argument X, For 16-bit input operands with a 14-bit fractional part, one bit of the integer part and sign bit at m 11 and 1 6, t, e, when splitting the range of variation of the argument 128 approximation intervals, each of which in turn is divided into 32 subintervals, the accuracy of determining the reciprocal value reaches the value and, eK 2, the device operates as follows. Upon the arrival of the first clock pulse at the input 11, the values of Y and X, presented in the additional code, are written to the input registers 1 and 2. In converter 12, the fractional part of the divider X is converted into direct code. At the address indicated by the m most significant bits of the fractional part X, represented in the direct code, from the node 14, the reference value of the reciprocal value C is selected, which goes to the output of the subtracted adder 15, at the same time at the address indicated by the 1 most significant and (n - m - 2) leading bits of the fractional part X. presented in the forward code, the value of V. is selected from node 13, which is fed to the input of the decremented adder 15. At In this case, B has a sign opposite to that of divider X. In adder 15, the reciprocal of the divider is calculated, which is the sum of X O, and the difference 20 15 25 35 Invention Formula " A device for dividing, containing the input registers of the dividend and the divider, the output register, two intermediate registers, a multiplication unit and a block for calculating the reciprocal, and the information inputs of the input registers of the dividend and divider are connected to the inputs of the dividend and divider of the device, respectively, the output of the input register of the dividend connected to the information entry the first intermediate register, the output of which is connected to the first multiplication unit, the second input of which is connected to the output of the first intermediate register, whose information input is connected to the output of the reciprocal calculation unit, the information input of which is connected to the output of the input divider register, the clock input of the device is connected to the clock inputs of the dividend and divider registers, intermediate registers and the output register, the information input of which is connected to the output of the multiplication unit, and the output to the output of unit, the computing unit of the reciprocal value contains two nodes of the tabular memory and the accumulator, the output of which is the output of the calculating unit of the reciprocal quantity, and the information inputs are connected to the outputs of the nodes of the tabular memory, which, in order to expand fields of application, due to the possibility of processing both positive and negative normalized numbers, a controlled transducer is inserted into the reciprocal calculation unit the additional code and the adder are algebraic; when the input of the controlled converter to the additional code is the input of the reciprocal calculation unit, the inputs of the second tabular memory node are connected to the outputs of the first and second groups of bits of the controlled converter into the additional code, and the inputs of the first The table memory node is connected to the outputs of the first and third groups of the controlled converter into an additional code and to the control input of the reciprocal calculation unit, which is connected to the output of the bit and the input register of the divider and is connected to the inputs of the control mode of operation of the control of the converter in the additional code and the adder.