SU1363186A1 - Arithmetic device - Google Patents

Abstract

The invention relates to computing and can be used to build high-speed operating devices of digital computers. The purpose of the invention is to increase speed by reducing the computation time of elementary functions. The proposed device consists of an arithmetic logic unit 1, a multiplier 2, a normalizer 3, two registers 4, 5 of general purpose, two buffer registers 6, 7, bus switch 8, multiplexer 9, register counter 10 of the memory address and block 11 permanent memory with the corresponding links. A high-speed device performs arithmetic-logic operations on operands specified in binary form. 1 il. (L with about: from 30 about:

Description

The invention relates to computing technology and to be used in the construction of high-speed operating devices of digital computers.

The purpose of the invention is to increase speed by reducing the computation time of elementary functions.

The drawing shows a functional diagram of an arithmetic unit,

The device contains arithmetic logic unit 1, multiplier 2, normalizer 3, first and second registers 4 and 5 of general purpose, first and second buffer registers b and 7, bus switch 8, multiplexer 9, register counter 10 memory addresses, block II fixed memory, information bus 12 connected respectively to the outputs of the arithmetic logic unit I of multiplier 2, normalizer 3, information inputs of general registers 4 and 5 and with the control output of the register counter 10 of the memory address, output 13 registries 4 obsh, vgo destination soy It is connected to the first information inputs of the multiplexer 9 and bus switch 8, the output 14 of the general purpose register 5 is connected to the second information inputs of the bus switch 8 and the multiplexer 9, the output 15 of which is connected to the information input of the register of the memory address counter 10, address output 16 which is connected to the address input of the block 11 of the permanent memory, the information output 17 of which is connected to the third information input of the bus switch 8, the first output 18 of which is connected by the information input 1. the first buffer second register 6-, the second output 19 of the bus switch B is connected to the information input of the second buffer register 7, the output 20 of the first buffer register 6 is connected to the first information inputs of the arithmetic logic unit 1, the multiplier 2 and the normalizer 3, the second information inputs of which are connected to the output 21 of the second buffer register 7, the inputs for the resolution of the general registers 4 and 5, the buffer registers 6 and 7: arithmetic logic logical codes

631862

block 1, multiplier 2, normalizer 3, register-counter 10 memory addresses, block 1 permanent memory. These and control inputs of the bus switch 8 and multiplexer 9 are connected respectively to the control bus 22 of the device.

The device works as follows.

10 way

The execution of the operation of addition, This operation is performed by the arithmetic logic unit 1, The operation begins with the failure of the source operands

If in the buffer registers 6 and 7. In registers 6 and 7, the operands can be written through the bus switch 8 of. registers 4 and 5 or from the fixed memory unit 11, for which the corresponding registers and control commands for the bus switch 8 are sent to the corresponding lines of the control bus 22. At the same time, the corresponding lines of the control bus 22 are sent to the arithmetic logic block 1 is provided with an operation code, such as a sum operation. Through the tact of the device to the outputs of the arithmetic logic unit 1

30 sets the value of the amount. This result can be selected from the device via data bus 12 or written to registers 4 and 5, with. corresponding control sigmav5t5 are fed to this via control bus 22.

ly,

The execution of the multiplication operation,, This operation is performed by multiplier 2. The multipliers are recorded in 40 buffer registers 5 and 7, from here through the information buses 20 and 21 go to the inputs of the multiplier. The senior and junior parts of the product are stored in the corresponding internal registers of the multiplier 2 and can be read alternately on the information bus 12, for which the corresponding operation code is supplied via the control bus 22

50 -..

Perform a shift operation. Shift

carried out by the normalizer 3 and the operand written in register 7, the shift parameter is fed either via busg gg not 20 or lib9 via control bus 22, and the corresponding opcode is fed through it. The result of the shift appears at the output of the normalizer 3 through the device operation cycle.

45

Perform normalization operation. This operation is performed by the normalizer 3, the normalizable operand comes from register 7, and the operation code is received on bus 22 simultaneously. Through the operation time of the device, the mantissa of a normalized number can be read from the output of the normalizer 3, and even after a clock time, the order of the normalized number can be read.

Perform division operation. The division operation is performed in two stages. At the first stage, the function of the inverse of the divisor is calculated. On the second - multiplication of the dividend by the reciprocal of the divisor. The operation of calculating the inverse function is based on the above operations: summation, subtraction, shift, normalization and multiplication, as well as auxiliary equipment: constant memory block 11, memory address register 10 and multiplexer 9. Original operands, the dividend and divisor are in registers 4 and 5. From this moment on, the first division stage begins - finding the reciprocal of the divider.

The divider through the bus switch 8 is entered into the register 7 and via bus 21 is fed to the input of the normalizer 3, which performs a logical left shift by k + 1 bit, which ensures the receipt of the value of m 2, which is written from the output of the normalizer 3 via the bus 12 In registers 4 and 5, at the same time, the memory addresses in register counter 10 through multiplexer 9 are inserted into the oldest k bits of the divider, which ensures that the address inputs of the lower part of block 11 are set to the permanent memory of the number corresponding to X ;, a to the address inputs of the older part of the software f 22 is supplied a control function of the reciprocal of the code. At the output of block 11 constant .pam is set to 1 / x

In the next step of the device operation, an analysis of the magnitude, y, is carried out. to zero. The value T-2 through the bus switch 8 is written to the register 6 and via bus 20 is fed to the input of the arithmetic logic unit 1, which performs the comparison operation to zero. In the case of a positive analysis result,

those. t-2. Oh, the first stage of the one-, radio division is over. The value of 1 / x; at the output of block 11, the side memory will be sought for the reciprocal function. This value is written to the register 7 via bus switch 8 and fed through bus 21 to the input of multiplier 2. At the same time, the dividend via bus switch 8 is written to register 6 and through bus 20 to the second input of multiplier 2, which performs the multiplication operation, the result of operation bus 12 is recorded in registers 4 and 5. In case of a negative analysis result, i.e. t-2 0, the arithmetic logic unit .1 performs on the operand m-2, which is present at its input, stored in register 6, an addition operation, i.e. 1-m 2, The result of this operation from the output ,, block -1 is written to registers 4 and 5. In the next clock cycle, the value 1-m 2 from registers 4 and 5 and the value 1 / x; from the output of the constant memory module M. through the bus switch 8 are recorded in registers 6 and 7, respectively, and on bus 20 and 21 are fed to the input of multiplier 2, which performs a multiplication operation, the result of multiplication is recorded in registers 4 and 5.

In the next clock cycle, the contents of the register-counter 10 of the memory address is increased by a unit of the least significant bit, which ensures that the output of the constant memory block is 1 / X ;. which is written to the register 7 via the bus switch 8. Parallel from the registers 4 and 5, the value is written to register 6. Bus 20 and 21, these values are fed to the inputs of multiplier 2, which performs the multiplication operation, 1 / x, -, the result is written via bus 12 to registers 4 and 5. In the next cycle, this value mi2 - 1 / x, -,, and

Parallel to it, the result of the previous multiplication (l-m 2) 1 / x; from registers 4 or 5 are written to registers 6 and 7, respectively, and buses 20 and 21 are sent to the input

 arif of methycological unit 1, which performs the operation of summation. At the output of block 1, the desired value 1 / x appears, which is entered into registers 4 via bus 12

and 5. In this, the first stage of the division operation ends. In the next device operation cycle, the values of the dividend and the inverse divider function from the outputs of registers A and 5 through the bus switch 8 are entered into registers 6 and 7 respectively and buses 20 and 21 are fed to the input multiplier 2. The result of the multiplier operation, which is the end result of the division operation, is recorded in registers 4 and 5. This completes the division operation.

Calculation of elementary functions. The elementary functions are calculated similarly to the operation of calculating a reciprocal function with the difference that the higher bits of the address of block 1 I fixed memory are supplied with the corresponding function code defining the area of the ROM containing the values of this tabulated function at the reference points.

Improving the speed of the arithmetic unit is achieved by reducing the time required to perform the operations of calculating elementary functions.

An example of calculating the inverse function.

It is required to calculate the inverse function given by the equation f (x) 1 / x, where the number x is normalized, t, e, 2 X 1 and has the id

 :( k 2, where N is the width of the operands being processed.

Argument change interval 2; l divide by dots into 2 intervals, where k is an integer less than N. The length of each interval (x, -; x ,,) will be

  ,

12

.

and the number of control points is p 2 +1. Since the value is not included in the interval for changing the argument, the number of control points for which the value of the function f (X;) is defined and stored in the ROM is equal to p, t, e, to address the ROM, k address bits, while the capacity of the ROM will be. N-bit numbers.

Such a partitioning allows the use of the formula for digital linear interpolation of a tabulated function for a small split interval to calculate the inverse function.

 n f (x;) +)) m + n

r, - (K «l)

where x; i X г х ,,, m X - X,, п х, ч «- X,

m + nx, v, - x; 2, then f ,,, (l-m-2-) - f (x;) + f,;. , (Y)

From this expression (1), it can be seen that the operation of calculating the inverse function is reduced to simple operations of shift, addition, and multiplus (

I.

Thus, in the proposed arithmetic unit, the operation of dividing and calculating the inverse will be performed on average

in time is 40% less than in the known device, and the time for calculating the elementary functions will vary in the same range as for the reciprocal function depending on the type of functions.

Claims (1)

Invention Formula Arithmetic unit, the arithmetic logic unit, the multiplier, the normalizer, the first and second general registers, the first and second buffer registers, the multiplexer and the block constant memory, and the output of the first buffer register is connected to the first information inputs of the arithmetic logic unit, multiplier and malator, the recording resolution inputs the first and second general registers, the first and second buffer registers, the control inputs of the multiplexer, the arithmetic logic unit, the multiplier and the normalizer are connected respectively to the control bus of the device, and the outputs of the arithmetic logic unit, the multiplier and the normalizer are connected respectively to the information a device bus, characterized in that, in order to improve speed by reducing the computation time of the elementary functions, a busbar is inserted into it. a switch and a memory address register counter, with the information inputs of the first and second general registers of destination being connected to the information bus of the device, respectively. 7 13631868 outputs - respectively with the first equating input of the unit with the constant second information inputs of the bus, the network is connected to the control bus switch and multiplexer, device, first and second outputs the output of which is connected to the information bus switch is connected by the corresponding input of the register counter to the information inputs The memory, the address output of the first and second buffer registers, is connected to the lower address input, the output of the second buffer registrar of the permanent memory, the control board is connected to the second, and the input information is connected to the information bus. The Q inputs of the arithmetic logic and logic block, the output of the block constant block unit, multiplier and normalizer are connected to the third information unit, and the register sync - the meter input of the tin switch, the memory address switch is connected to the control input of which is connected to the control bus of the device with the control bus of the device, up-va.