SU662938A1 - Divider - Google Patents

Description

 ., V. /; ;:,: G. ; -; ; .. The invention relates to the field of computer technology and can be applied and digital computing machines, specialized digital computing devices, and computational environments built on large integrated circuits. .V A device is known for dividing in which the execution time of division operations is PrO, η ij. The disadvantage of the known device is a low-speed performance in real time, .. The closest in technical essence to the proposed device is a device containing an adder, a divider register, a divisor register, a de scrambler, an OR element, a register of chg. The first and second control inputs of which are connected respectively to the first and second outputs of the decoder, the outputs of which are the outputs of the device, the output of the OR element is connected to the first control input of the divider register, whose outputs are connected to the first group of information inputs of the adder, the first and the second inputs of the decoder are connected to the direct and the inverse respectively; vyh6d6m; sgga5) shego razryaYaa-sumator G2). . ...: Inadequate device 6 is downstream. The purpose of the invention is to increase the speed of the device. For this purpose, a trigger has been entered into it. The outputs of the register DB register are connected to the second group of inputs of the adder, and the first and second information inputs of the register bank connect to the first AND coo information of the controller, and the inverse outputs of the senior section of the totalizer, and the inverse outputs of the senior size of the totalizer, and the inverse outputs of the senior size of the totalizer, and the inverse outputs of the senior digit of the totalizer, and the inverse outputs of the senior digit of the totalizer, and the inverse outputs of the senior digit of the totalizer, and the inverse outputs of the senior bit of the adder and the inverted outputs of the senior bit of the totalizer, and the inverse outputs of the senior digit of the adder and the inverter outputs of the higher bit of the totalizer, and the inverse outputs of the senior digit of the adder and the third inputs of the control of the splitter is not the first and second. In the case of the trigger, the first and second outputs of which are connected respectively with the third and fourth decoder, the third and fourth information buses connect The first control bus is connected to the control input of the adder and the fourth control input of the register of the divider, the second control bus is connected to the first input of the element OR, corresponding to the first and second groups of information inputs of the register divider and private register. , by the counting input of three years, in the course of n {"is not a register divisible and the third control of the private register, IrpeTlbH control is connected to the second input of the element OR, the fifth input of the control Giustra divider, a fourth input register of the private control. The drawing shows a structural diagram of the proposed separating device. The device contains (p + 6) bit summation block 1 (n-bit width of source operands), (n + 3) bit register 2 divider, n-bit register of divisible 3, bit register 4. quotient, trigger 5 , de-integrator 6, element OR 7, information buses 8-11, outputs of the device 12, 13, control buses 14-16. Summation block. 1 has a two-way left shift circuit. Registers 2,3 and 4 have chains of handlers. direct and auxiliary codes and shift chains one bit to the left. Register 2 and 4, in addition, have a circuit receiving code. The lower bits of registers 2 and 4 are the summation of the registers, and the remaining bits of these registers have a transfer distribution chain. The decoder 6 can be built in accordance with the system of transitions: к) other useful functions of the form: ft ft 7 where fi is the function of the i-ro output () of the decoder b; p is the value of the highest bit. The sum of the summation block 1 with weight is the value of the state of a trigger, 5. , The initial operations A and B and the result X are represented by binary redundant IODOM with the numbers 1,0,1. In this case, the operands and in and the result of X have the form: A.E a; 1-1 f.-. 1 | de a, b | ,, 0, ij. ii .. Each digit of the number in the redundant representation is encoded with two digits. Of the sets T, O, y. At this digit T corresponds to a signal at Vksd B or 10, or at output 12. Digit 1 corresponds to the signal at input 9 or 11, or output 13. At figure 0, there is no signal at input 8.9, at inputs 10.11 or at the outputs 12.13. The codes of the divisible A and the divider B are located at the same time at the inputs 8.9 and 10.11 simultaneously, i.e. at each moment of time the inputs of the divisor and divider bits with the same weights are received. The following constraints are imposed on the values of and and B:, L | 2i & i. The principle of operation of the device is as follows. In the initial state in the lower order of the register 3, the unit is recorded, and all other registers, the summation block 1 and the trigger 5 are set to the zero state. In each cycle of calculations, the clock inputs 14, 15 and 16 are alternately received by the clock signals y, U2 and UZ. By the beginning of each i-ro cycle of computations (, 2 ... n + 3), the digits of the next bits, respectively, aj and bj, are received at the inputs 8.9 and 10.11. In the first cycle of the division cycle, the signal y from input 14 enters the shift circuit of summation unit 1 and the reception circuit of register code 2. As a result, the contents of summation unit 1 are shifted two digits to the left, and the value of next bit bj. If (signal is present at input 10), then one is subtracted from the low-order bit of register 2. If (signal is present at input 11), then one is added to the low-order bit of register 2, and if (signal at inputs 10 and 11 is missing) then register 2 does not change its state. Thus, in register 2 there is accumulation of divider B. In the second cycle of the division cycle, the signal y from input 15 enters the reception circuit of the trigger code 5, through the OR element 7 enters the output circuit of the register 2 codes and the output circuit of the codes and shift of the registers 3 and 4. As a result, in the summation block 1, the contents of this block are summed with the codes from the outputs of registers 2,3 and 4, and the trigger 5 records the previous state of the high bit of the summation block 1 (simultaneous summation in the summation block 1 and recording P The previous state of the most significant bit of this block in trigger 5 is possible, since summation block 1; is shifting and, therefore, each bit of this block must be built on a pair of flip-flops or on triggers with an internal delay) at the outputs of register 2 it depends on the previous state of the most significant bit (sign) of the summation block 1. If a zero (positive sign) is written in this bit, then an additional code is output from register 2, and if this bit is a single unit (negative sign ), then from register 2 to the sum block world 1 is transmitted direct code. The code at the outputs of register 3 depends on the signals at inputs 8 and 9. If a signal is present at input 8 (), then an additional code is output from register 3, and if there is a left-hand signal at the output 9 (ajsl), a direct code is issued. If there are no signals at inputs 8 and 9, the code from register 3 is not issued. The number of outputs of register 4 depends on the values of the signals at inputs 10 and 11. If there is a signal at input 10 (bj-T), then a direct code is output from register 4, and if there is a signal at input, the stroke "11 ()" additional code. In the absence of signals at inputs 10 and AND the code from register 4 is not issued. At the same time, the contents of the registers 3 and 4 are shifted one time row to the left (simultaneously issuing codes from these registers and shifting their contents are possible, since registers 3 and 4 are shifting and therefore each bit of these registers must be built on a pair of flip-flops or on flip-flops with an internal rear view). When issuing an additional code from registers 2.3 and 4, single signals are sent to the inputs of the free (not associated with the outputs of registers 2.3 and 4) bits of summation 1 and, besides, the younger bit is served one signal unit. Before the beginning of the third cycle of the calculation cycle, Dahlfra Torb analyzes the status of trigger 5 and the highest bit of the summation block 1 and the code for the next bit of quotient x, which arrives at outputs 12 and 13 of the quotient, appears at the outputs of the decoder B. In the third cycle, the dividing signal y from input 16 goes to the receive circuit of register 4 code, to the shift circuit of register 2 and through the OR 7 element to the output circuit of register 2 codes. As a result, from register 2, in accordance with the value of the highest the (sign) bit of the summation block 1, in the summation block 1, wf is directly or additional code, and the lower order of register 4 adds the value of the next bit x (. In this case, if there is a signal at output 12 (), then the unit is subtracted from the UT of the lower register bit 4. If a signal is present at output 13 (), a unit is added to the slowdown register bit 4, and if the signals at outputs 12 and 13 are missing 1 (xjsO), then register 4 does not change its state. Thus, in register 4 there is an accumulation of private X. At the same time, the contents of register 2 are shifted by one digit to the left. This completes one calculation cycle. The quotient with a weight of 2 appears after 388 in the calculation cycle after the arrival of the dividend And the divider with a weight of 2. Therefore, to obtain a quotient with an accuracy of 2, it is necessary to perform n + 3 cycles calculated . Consider the operation of the device by example. Let L (25 / b4 dec. (0.11 | 111) gg., B a (43 / b4) dec. (O, 111011) gg. For these operand values, therefore, you must perform 9 calculation cycles. The calculation process is illustrated by the table states of the summation block, registers, and trigger of the device. Result of the calculations for these values of the source operands (001.10111T) electr (3.7 / b4) dec. From the considered example it is clear that to get the result with the exact 2-n Calculation cycles. The speed ratio of the known and proposed device is: If we take pa (32, which is Consequently, the performance of the proposed device is 1.8 times higher than that of a known device when operating in real time.We determine the delay introduced by K devices when using them in the computing environment. and a divider with a weight of 2 f, the discharge of a quotient with a weight of 2 appears after 3 cycles of calculations. Thus, the next bit received at the output of the device is processed by another device in the next cycle, the trace quently delay introduced by one device, is 4 cycles. The delay introduced by the devices will be-cycles. Thus, the gain in speed when used in the computing environment of the proposed device as compared with the efficient one will be limited by the expression: FAL. П (К + 1) 4К-Г With nfe32, the use in the computing environment of the proposed device permits an increase in speed by 32/44 8 times.

662938

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