SU903866A1 - Conveyer multiplying device - Google Patents

Description

one

The invention relates to computing and can be used in the construction of high-performance processors of digital computers. - J

A multiplication device is known comprising a random number sensor, a comparison circuit, counters, gates, and a delay element lJ.

However, such a device has low performance, its speed is limited to the waiting time for the completion of the multiplication operation before entering subsequent pairs of operands.

It is also known a multiplication device containing a matrix of elements, a multiplier and a multiplier registers and an adder 2.M

However, this device also has a low-speed, since. operand cycle cannot be

less time to complete the operation of the Kenya smart.

Claims (2)

The closest in technical essence to the invention is a con-; voyero multiplying device containing an array of adders of dimension N хН (where, n-1 is the size of factors, M N + 1), the first row of the matrix contains N adders, each the next row of the matrix contains M adders, the last column of the matrix contains N-1 totalors each. The previous column of the matrix contains N adders, N + 3 multiplier registers, M multiplicative registers, each of which is divided into N subregisters, the buffer register, which is divided into N subregisters The inputs of the first multiplicated subregisters are connected to the corresponding bits of the first information bus, the outputs of the (i, j) th multiplicand subregister are connected to the inputs of the (i + 1, j) -ro sub multiplier of the multiplicand (i 1, ..., N j. 390 1, ..., M), the inputs of the buffer subregisters are connected to the corresponding outputs of the N senior accumulators of the last row of the matrix, the outputs of the adders of the last row of the matrix are connected to the output bus of the device, the inputs of the first multiplier register are connected to the corresponding bits of the second informational bus, reg-outs The factor of the multiplier (, ..., N + 3) of PDA is connected to the inputs of the (i + l) -ro register of the multiplier and to the control inputs of the corresponding N ml-associated summers of the 2j matrix. In a known conveyor multiplier device, operands can be entered into a multiplier in a clock cycle equal to the end time of the work of ONE group of adders of the matrix, i.e. the pitch of the subgroup, the group of bits of the operands is determined by the successive work of two adders that make up the group. The purpose of the invention is to increase the speed of the device. The goal is achieved by entering N transfer registers into each row of the device matrix, N partial amount su registers entered in the first matrix row, N + 1 partial sums registers entered into each subsequent row of the matrix The outputs of the i-ro buffer sub-register (i 1, .., N) are respectively connected with the lower information inputs of the adders of the first row of the matrix, the outputs of the sum (j, i) -ro adders (, .., N-1, j 1, ... M) bitwise connected to the inputs of the corresponding the partial sum register, the outputs of which are respectively connected to the lower information inputs (i + 1, j) -ro of the matrix's matrix, N-1 lower outputs (i, j) -ro of the subregister of the multiplicand (i -1,..., M- 1, j 1, .. ,, N) bitwise connected to the senior informational inputs (i, J) -ro of the adder, ...,, .., N), senior output (i, j) -ro of the subregister multiplicand (2, ..., M, j 1, ..., N-1) is connected to the senior information input (|, j + 0-ro sum TOpaCi 1, ..., N,, ..., N matrix, the output of the transfer of each adder matrix, except for the adders of the last column, connected to the input of the corresponding register wasp, output (i, j) -ro of the transfer register (i 1,. ,,,, N, j 1 ..., N), except the last one in the first row of the matrix, is connected to the transfer input (- /, J + 1 ) th matrix adder, the output of the last transfer register is connected to the information input of the last. Summer of the second row of the matrix, the inputs of the first subregisters of the multiplicand are connected to the outputs of the corresponding last subregisters of the multiplicand. The drawing shows a block diagram of the device. The conveyor multiplying device contains a matrix of adders 1-19, transfer registers 20-35, partial sum registers, multiplier registers 50-56, multiplicand registers 57-61, buffer register b2, output bus 63, information buses 64 and b5. The subregisters 57-61 of the multiplicand are divided into N subregisters (, the multiplicity of the factors) in each row of the matrix. Buffer register 62 is divided into N sub-registers. In the device, the inputs of the sub-registers 57157 “4 multiplicands are connected with the corresponding bits of the information bus and, accordingly, with the outputs of the sub-registers device .1-gb1. the multiplicand, the outputs of the subregisters, 57.IT 57. the multiplicand are connected bitwise with the inputs of the subregister 5 .. multiplicand, the outputs of which are connected bitwise with the inputs of the subregister 59-1t59-multiplicand, the outputs of which bitwise are connected to the inputs of the subregister 60.1; 60.4 multiplicable whose outputs are posed with the inputs of the BT.TGB sub-registers. multiplicable, the inputs of the buffer sub-registers B2: -b2.4 are connected to the corresponding outputs of the adders 16-19, the outputs of the adders 15-19 are connected to the output bus 63 of the device, the inputs of the multiplier 50, are connected to the corresponding bits of the information bus B5 , the outputs of the register multiplier 50 bitwise connected to the inputs of the register 51 multiplier, the outputs of which are bitwise connected to the inputs of the register 52 of the multiplier, the outputs of which bitwise connected to the inputs of the register 53 multiplier, the outputs of which are connected bitwise from the input multiplier and the register 5, the outputs of which are connected to the inputs of multiplier register 55, which outputs are connected bitwise with the inputs of the multiplier register 5b, the register outputs are connected to the multiplier 505b controls the adders 1-8, 10-13 yuschimi inputs. 15-18 multiplication matrix, the outputs of the buffer sub-registers 62, If62, respectively, are connected with the lower information inputs of the adders 1-matrix, the outputs of the sum of the adders 1-1C are bitwise connected with the inputs of the corresponding registers 36-49 of the partial sum, the outputs of which are respectively connected with the younger information inputs 5-19 matrix adders, N-1 junior outputs of the subregisters 57.1: 61.M multiplicand bitwise are connected to the senior information inputs of the corresponding adders 1-19 of the matrix, senior outputs of the subregisters 58. 58.3, 59..3, 60.1tbo.Z , 6l.H6l. multiply connected to the information inputs of the corresponding adders 2-4, 6-8, 11-13, 16-19, the transfer outputs of the adders 1-8, 10-13, 15 are connected to the inputs of the respective transfer registers 20-35, the outputs of the registers 20-22 , 24-35 are connected to the input p. Renos of the corresponding sum (matrix tori 1-19, output-transfer register 23 are connected to the information input of the matrix adder 9. The device architecture presented implements the multiplication conveyor method by stepwise adding partial sums of the product with left shifted multiply by one bit gated by an appropriate multiplier. The device operates in four steps as follows: Step one. The first clock pulse coming from the central control unit of the digital computer via information buses 65 and 64 to register 50 and sub-register 57.1, respectively, are taken as lower four the multiplier and multiplicand bit, the multiplicand from the sub-register 571 is fed with a shift of 1 bit to the left to the corresponding inputs of the adder 1, and the low-order bit of the multiplier to its gate input .. At the adder 1, addition occurs obedient buffer sub-register 62.1 (equal to zero in the first cycle) with the contents of the sub-register 57.1. the registers are circled by a dotted line) and are simultaneously fed to the four-bit input of the adder 5 of the second row of the multiplier and the transfer input of the adder 2 of the first row of the multiplier. At the same time, the contents of sub-registry 57.1 are accepted by sub-registrar 5§.1. The lower three bits from its output to provide the necessary shift are fed to the corresponding inputs of the adder 5 and the leading bit of the subregister 58.1 to the lowermost bit of the corresponding input of the adder 2. In the subregister 57.1, the multiples of the next pair of operands are accepted and fed into the adder 1, into the subregister 57-2 are received via buses 64. The second four bits of the multiplicable first pair of operands are fed to adder 2 with a corresponding shift. To the other inputs of adder 2, the contents of buffer sub-register 62 are fed. 2. The contents of register 50 are replaced by bits of the multiplier of the second pair of operands. Register 51 receives the contents of register 50 and the low order multiplier is fed to the gate input of the adder 2, and the next time / p to the gate input of the accumulator 5- The third clock pulse provides input to the multiplier of the subsequent four bits, the corresponding information, its promotion in the manner described above in registers 50, 51, 52 and 57, 58, 59, and the partial amount corresponding to the eight bits with two carry bits is fixed in registers covered by dotted line II. The fourth clock pulse forms a twelve-bit bottom with three carry bits, a partial sum of the first pair of operands in the registers covered by the dotted line Ml. From the geometrical arrangement of the dotted lines I, II, III, the further distribution of the result distribution front can be seen. By the fifth TSKTOBbiN pulse, the low bits of the result from the output of the first adder 15 of the last row are output to the device to ensure that the calculations are performed with double precision. The senior bits of the sub-registers 60 through the sub-registers 61 are fed to the corresponding adders of the last row. By the same clock pulse, register 50 and sub-register 57.1 add the lower four bits of the multiplier and the multiplicand n to the operands. The second step. The next clock pulse results from the output of the adder 1b is written to the buffer sub-register 62.1 and from its output the result goes to the adder 1. The code multiplied from the sub-register 61.1 is received by the sub-register 57 where the next multiplier of the first pair of operands is received in the register 50 . The second and third steps are carried out similarly to the first one and differ in the groups of bits located in the multiplier register. Fourth step. In the fourth step, the result is corrected on the last row of the adders. This is possible because the multiplier codes contain 1 bits and in the fourth step the last row of adders is not occupied. From the multiplier, the result is cleverly read. four bits with a cycle equal to the time of signal propagation in one four-bit adder, this provides twice the clock frequency of the multiplication in the stream compared to the known device. In addition, with noMOUv, it is possible to simultaneously perform five multiplications, each of which is performed by the above method in four steps. : Thus, the inclusion of registers for storing partial sums and transfers to the output of each adder allows halving the cycle of supplying operands to the device input without significant hardware costs, thereby increasing productivity, and as a result, the efficiency of the multiplying device. Claims of the invention Conveyor multiplying device containing the matrix of adders of the dimension NxM (where N, n-1 times 68 are the factors, AND N + 1), the first row of the matrix contains N adders, each subsequent row of the matrix contains M adders, the last the matrix column contains N-1 adders, each previous matrix column contains N adders, N + 3 multiplier registers, M multiplicative registers, each divided into N subregisters, a buffer register which is divided into N subregisters, and the inputs of the first subregisters multiply The first one is connected to the corresponding bits of the first information bus, the outputs (i, j) of the multiplier sub-register are bitwise connected to the inputs (i + 1, j) of the sub-register of the multiplicand (.1 1, ..., N, ... , M) 9 inputs of the buffer subregists are connected to the corresponding outputs of the N senior accumulators of the last row of the matrix, the outputs of the adders of the last row of the matrix are connected to the output bus of the device, the inputs of the first multiplier register are connected to the corresponding digits of the second information bus, the i-ro outputs of the multiplier (i 1, ...,) porazh bottom connect Eny with inputs of the (i + 1) -ro multiplier register and with the control inputs of the corresponding N low adders of the matrix, which, in order to improve speed, entered into each row of the matrix N transfer registers, entered into the first row of the matrix N registers of partial sums, in each subsequent row of the matrix, except for the last, N + 1 registers of partial sums are entered, and the outputs of the i-ro buffer subregister (G, ..., N) are respectively connected to the lower information inputs of the adders of the first row of the matrix, outputs sums (i, j) -ro sum Hur (i 1,. . . , N-1, 1, ..., M) bitwise connected to the inputs of the corresponding register of the partial sum, the outputs of which are respectively connected to the lower information inputs (I + 1, j) -ro of the matrix adder, the lower outputs (i, j) The subregister of the multiplicand (i + 1, ..., M-1,,.,., N) is bit-wise connected to the old information inputs (i, j) -ro of the adder (i 1, ..., N,,. .., N), the high output (i, j) -ro of the subregister of the multiplicand (,, .., M, j 1,., .., N-1) is connected to the high information input (i, j + 1) - ro adder (, ... sN,, ..., N) of the matrix, you