SU1023324A1 - Device for computing logarithm of binary number - Google Patents

Abstract

A device for calculating the logarithms of binary numbers, containing two registers, a group of elements 2I-OR, the device input is connected to the input of the first register, the inverse output of the second register is connected to the first information input group of elements 2I-OR, characterized by the fact that, in order to improve speed it additionally entered three registers, four adders, a clock pulse generator. The trigger and (and-2) computing blocks of the iteration, where V) is the width of the input number, the output of the i-th bit of the first register is connected to the input of the (i + 2) bit of the second register, the second information input of the group of elements 2I- OR is connected with a shift of two bits to the right to the output of the third digit of the third register, the direct output of the first digit of which is connected to the first control input of a group of elements 2I-OR, the second control input of which is connected to the inverse output of the first digit third register, the output of the i-th bit of the first reg country connected to the first input U + 1.) - bit and the second input of the i-th bit of the first accumulator, the output of which is connected to the information input of the third register, the output of which is connected to the first information input of the second Adder, the second information input of which connected to the output of a group of elements 2I-OR, the inverse output of the first discharge of the third register is connected to the first input of the third adder, the inverse output of the trigger is connected to the first input of the fourth adder, the second input of which is connected to the output of the fourth the fourth register, the output of the fourth adder through the fifth register is connected to the output of the device, in each numeral iteration block containing three registers, a group of elements 2И-OR and two adders, the inverse output of the first register is connected to the first information one. the input of a group of elements 2I-OR, the output of the i-th digit of the SECOND register; dinene with the first information input of the first adder and c (-i + j +2 is the size of the second information input of the group of elements 2I-ILN, where is l, 2, ..., m (i is the bit number of the register), 1, 2,.,., AND () is the number of the computing iteration unit), the output of the group of elements 2И-OR is connected to the second information input of the first adder, the first governing input of the group of elements 2И-OR is connected to the direct output of the first bit of the second register- inverse. The input is connected to the second control input of the 2I-OR group and the first input of the second adder, the second input of which is connected to the output of the third register, in addition; the i-th bit of the group of the 2I-OR device is connected to the input (- 1 +1) bit of the first register of the first computing block of the iteration, outputs of the second and third adders of the device are connected respectively to the inputs of the second and third registers of the first computing block of the iteration, output of the i-th bit of the group of elements 2I-OR previous its computing.

Description

the iteration block is connected with the input -i + l) -ro bit of the first register of the subsequent iterative computing block, the outputs of the first and second adders of the previous computing iteration block are connected respectively to the inputs of the second and third registers of the subsequent computing iteration block, the output of the first bit the first adder (ii-2) -ro computing unit iteration connected to the information input of the trigger, the output of the second adder (and 2) -th computing unit iteration connected to the input of the fourth register of the device, in Ora third input cyiviMaTopa, devices and third inputs of second adders each calculator, Nogo iteration unit connected with the bus logic zero, control inputs of all registers and flip-flop connected to the output of the clock.

The invention relates to computing technology and can be used in universal and specialized digital computers for logarithmic large arrays of multi-digit numbers.

A digital device for logarithmic binary numbers is known that contains two adders, a shift register, an I-LLL circuit, an AND circuit, a trigger, a storage unit, and a control unit 11.

The disadvantages of the known device are low speed, as well as the need to store constants in the memory.

Closest to the invention is a logarithmic and inverse reproduction device, containing three registers, a counter, two AND-OR 2 cards.

 A disadvantage of the known device is low speed.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that in a device for calculating by a logarithm of binary-r numbers, containing two registers, a group of elements 2I-IL the device input is connected to the input of the first register ,; the inverse output of the second register is connected to the first information input of a group of elements 2I-OR; three registers, four adders, a clock generator, a trigger and (and -2) are additionally entered in the iteration number blocks, where the input number is the bit of the first register is connected to the input (-i +2) of the bit of the second register; the second information input of the groups of elements 2I-OR is connected with a two-digit shift to the right to the output of the -th bit of the third register; direct output of the first bit which is connected to the first control input of the group of elements 2I-OR, the second control input of which is connected to the inverse output of the first bit of the third register, the output i of the first register bit is connected to the first input () of the bit and to the second input of the 1st bit the first adder, the output of which is connected to the information input of the third register, the output of which is connected to the first information input of the second adder, the second information input of which is connected to the output of the group of elements 2И-OR, the inverse output of the first bit of the third regis Pa connected to the first input of the third adder, the inverse output of the trigger is connected to the first input of the fourth adder, the second input of which is connected to the output of the fourth register, the output of the fourth adder through the fifth register is connected to the output of the device, in each iteration computing unit containing three registers, a group elements 2И-OR and two adders, the inverse output of the first register is connected to the first information input of the group of elements 2И-OR, the output of the second section of the second register is connected to the first information input m of the first adder and cf-iIj H-2) by the bit of the second information input of the group of elements 2I-OR, where (1 1,2,.,., t) i is the bit number of the register, С, ...,} j - the number of the computing iteration block, the output of the group of elements 2I-OR is connected to the second information input of the first adder, the first control input of the group of elements 2I-OR is connected to the direct output of the first bit of the second register, whose output is connected to the second control the input of the group, the elements 2I-LNI and the first input of the second sum1.1ator, the second input of which is connected to you The third register one, besides, the output of the i-th bit of a group of elements 2I-OR devices is connected to the input (1 + 1) -th bit of the first register of the first computing block of the iteration, the outputs of the second and third summaries are connected respectively to the inputs the second and third registers of the first computational iteration block; the output of the i-th bit of a group of elements 2I-OR of the previous computational block of iteration connected to the input (-i +1) of the first register of the subsequent computational block of iteration / outputs of the first and the second the adders of the preceding computational iteration block are connected respectively to the inputs of the second and third registers of the subsequent iterative computing tree, the first bit of the first adder (and -2) -th computing iteration block is connected to the trigger information input, the output of the second adder | vi-2) the computing block of the iteration is connected to the input of the fourth register of the device, the second input of the third cyi taTOpa device and the third input of the second adders of each computing block of the iteration are connected to the bus l th well, control inputs of all registers and flip-flop connected to the output of the clock. The drawing shows a block diagram of the device, the Device will save registers 1-5, adders 6-9, a group of elements 2И-OR 10, trigger 11, ("-2) computing unit 12 iteration, each of which contains registers 13-15, group elements 2I-YLI 1-6, the adder G7 and 18, as well as the generator 19 clock pulses. The device is designed to calculate the function of normalized numbers, represented in the fixed-point format. The calculation algorithm is described by the following iterative formulas N. .-) -fe.Vl. About 1 1. . , (), to. f h. eslm Hch7 / -; TI I O, if Xi j which, at the initial values of O,% O, give after the iterations of water. The device consists of steps, each of which carries out one iteration of the computational process. The number and is equal to the size of the numbers to be processed. The device works as follows. In the first cycle, the number X enters the input register 1. The contents of register 1, as well as its contents, shifted one bit to the right, are blunt by adder 6, and VoH + (l-) is formed from Buxjo ie. In the second clock cycle, the contents of register 1, shifted by two bits to the right, are written to register 2,. And the value of Hh from the outputs of adder 6 to register 3. If y = 1, i.e. the first bit of the register; 3, displaying the integer part of the number X, zero, then the signal from the inverse output of the first bit of register 3 causes the iipo-walk to the adder 7 through the group of elements 2I-OR 10 of the contents of register 3, shifted by two bits to the right i.e. . If X;, /, then the signal from the direct perHctpa 3 discharge output through the 2Y-OR 10 element group passes the inverse register 2 content value equal to - Xo. Thus, the value is formed in the 2I-OR 10 element group. This value is fed to the adder 7, where sum-. It is aligned with the contents of register 3, equal to X. At the adder 7, the value X is generated. Filing the contents of register 2 to the reverse-adder 7 with a code permits replacing the subtraction operation with an addition operation. . The constants eog ,, + 2-) (1 + 2 / are formed at the inputs of the summator 8. The constant BoQ. 1) in the binary code has a value of 0.100101011100,. and the constant Bog (i + 2) is 0.010100100111. Here it is assumed that n 12. For their formation | 1 and in discharges. the adder, where the value of the bit of the Constant, you are equal to one, is fed the inverse of the first bit of register 3. If X-i 1, then in these bits will go, units go; if X 7/1, then zeros. The remaining bits of the adder are grounded, i.e. their input is constantly fed the value of the logical p. Thus, on the adder 8, the value of the same cycle is formed in the input register 1, the second element of the array enters, and above it p. the operations that were performed in the first clock cycle over the first operand are disturbed. B. In the third clock cycle, the value of 1 # from the group of elements 2I-OR 10, shifted by bit to the right, is written to register 13, to registers 14 and 15,. respectively, the values from the outputs of the adders 7 and 8 are recorded. In the group of elements 2I-OR 16 of the first computing unit 12, the value E is formed on the adder 17 -. Xj, on cyivD / iaTope 18 — the same tact in registers 2 and 3 records intermediate results of processing the second element of the array, the second iteration is performed on the second stage of the device, and the third sjjement of the array being processed goes to the input, and above it produced as described. In the i-th cycle on the adder 9, the contents of the register 4, equal to - vj - i t with a constant. (+,), Is added, which is formed by submitting the inverse trigger value 11, (and + 1) -th bit of the adder, equal to the value of the first bit) c and the ground of the remaining bits. The resulting value is% B (It enters the output register 5 and out of it to the output of the device. At the same time, the results of processing all subsequent elements of the array are shifted down one step and are processed further.

The result of processing the first element of the array is obtained through w clock cycles, and each subsequent element of the array - through one clock cycle.

The clock pulses controlling the operation of the device come from a generator of 19 clock pulses.

With the arrival of each pulse, information from the previous stage of the conveyor is written into the registers of the next stage. The frequency of the clock pulses is determined by the conveyor clock, which is equal to the delay in one of its stages Tjj tcM- W, where t is the time of the addition of two numbers on the totalizer; delay of information by a group of elements 2I-OR.

0 Since the device operates according to the conveyor principle, its speed at. The processing of arrays of binary numbers is determined by the TO pipeline clock.

The technical and economic efficiency of the present invention, with, is that the device has a high homogeneity of the structure, which

0 allows it to be implemented in the form of large integrated circuits, as well as the fact that the device operates according to the conveyor principle, which makes it possible to significantly increase the speed of the device.

Claims (1)

DEVICE FOR CALCULATING Binary NUMBER LOGARITHMES, containing two registers, a group of 2I-OR elements, the input of the device is connected to the input of the first register, the inverse output of the second register is connected to the first information input of the group of 2I-OR elements, which differs in order to improve performance in three registers, four adders, a clock pulse generator, a trigger, and (and-2) iteration processing units, where b is the bit depth of the input number, and the output of the ith bit of the first register is connected to the input (i + 2) -discharge of the second register, the second information input of the group of 2AND-OR elements is connected with a shift of two bits to the right to the output of the i-th category of the third register, the direct output of the first category of which is connected to the first control input of the group of elements 2I-OR, the second control input of which is connected to the inverse output of the first discharge of the third register, the output of the i-th discharge of the first register is connected to, the 'first input <4 + 1.) - the discharge and to the second input of the i-th discharge of the first. adder, the output of which is connected to information input of the third register whose output is connected to the first information input of the second An adder, the second information input of which is connected to the output of the group of 2I-OR elements, the inverse output of the first discharge of the third register is connected to the first input of the third adder, the inverse output of the trigger is connected to the first input of the fourth adder, the second input of which is connected to the output of the fourth register, the output of the fourth adder through the fifth register is connected to the output of the device, in each iteration block containing three registers, a group of 2-OR elements and two adders, the inverse output of the first register is connected to the first informational '.' the input of the group of elements 2I-OR, the output of the i-th category of the second register is soy-; dinene with the first information input of the first adder and c (i + j + 2 / -digit of the second information input of the 2I-OR group of elements, where -i = 1,2, ..., m (i is the register bit number), j = 1,2, ..., ¼ (4 is the number of the iteration computing unit), the output of the 2-OR element group is connected to the second information input of the first adder, the first control input of the 2-OR element group is connected to the direct output of the first discharge of the second register, inverse: the output of which is connected to the second control input of the group of elements 2 AND-OR and the first input of the second. Gf 00 co GF adder ', the second input of which is connected to the output of the third register, in addition, the output of the ί-th category of the group of elements of the II-OR device is connected to the input of the (4 +1) -th category of the first register of the first iteration computing unit, the outputs of the second and third adders the devices are connected, respectively, to the inputs of the second and third registers of the first computing iteration block, the output of the ith discharge of the group of 2I-OR elements of the previous computing one. the iteration unit is connected to the input of 'Vi + l) - ro of the discharge of the first register of the subsequent iteration computing unit, the outputs of the first and second adders of the previous iteration computing unit are connected respectively to the inputs of the second and third registers of the subsequent iteration computing unit, the output of the first discharge of the first the adder of the (and-2) -th iteration computing unit is connected to the information input of the trigger, the output of the second adder (and-2) -th iteration computing unit is connected to the input of the fourth device register, second th third adder input, a third input device and second adders each iteration of the computing unit connected with the bus logic zero, the control inputs of all registers and flip-flop connected to the output of the clock. 12