SU1032453A1 - Device for multiplying - Google Patents

Abstract

A DEVICE FOR MULTIPLICATION containing the register of multiplicable, i blocks for calculating the bit values of the product (Y is the number of multiplicable bits), the buffer registers of the first and second groups, and the input of the first factor of each block for calculating the bit values of the register is connected to the output of the corresponding register register , the input of the second factor of each block for calculating bit values of the product is connected to. The tt INPUT of the device multiplier, the outputs of the lower and higher bits of each block for calculating the bit product values are connected to the inputs of the corresponding buffer registers of the first and second groups, the output of the first buffer register of the second group is connected to the output of the device, in order to improve speed , the device additionally contains a group of adders, and the inputs of the h-th adder of the group (, 2, ..., m-1) are connected to the outputs of the i-th buffer register of the first group and (-1 + 1) -th buffer register the second group, the inputs of the i-th group adder are connected to the output of the i-th buffer register of the first group and the device correction input, the output of the sum and transfer of each group adder are connected to the inputs of the first and second lower-order terms of the corresponding unit for calculating bit product values. t

Description

The invention relates to the WELECHANICAL technique and can be used in the development of high-speed devices for multiplying the numbers represented in any positional number system. Its application is especially effective when using large integrated circuits. A multiplication device is known that contains a drive (a photoluminescence unit) and multiplies X multiplier by a factor of N 1:) and g f, and multiply X is added to a previously cleaned accumulator X once again, then it is shifted to the left by one bit and again However, S2 is used. and so on until / until all bits of the number have been processed. The disadvantage of the device is its low speed. The closest to the proposed PS of the technical entity is a multiplication device containing a multiplicative register, and blocks for calculating product bit values (AND is the number of multiplicable bits), AND the buffer registers of the first group and the c buffer registers of the second group, and the input of the first factor of each the unit for calculating the bit values of the product is connected to the output of the corresponding bit of the register of the multiplicand, the input of the second factor of each block of the calculation of the bit values of the product is connected to the input of the multiple the device residents, the inputs of the first and second terms of the lower bit of each block for calculating discharge product values are connected to the moves of the corresponding buffer registers of the first and second groups, the outputs of the low and high bits of each block for calculating bit product values are connected with the inputs of corresponding buffer registers of the first and second groups, the output of the first buffer register of the second group is connected to the output of the device, the input of the second and the last last block for calculating bit values products are connected to the correction input of device 2. This device is intended to multiply numbers in an arbitrary positional number system with the knowledge of N 2, in particular, in a coded number system with a base of N Tv-ary bits. are grouped by K, where K is an integer and greater than one. The disadvantage of such a device is a relatively low quick action. This is due to the fact that / in order to increase the SPEED of multiplying numbers in a known device, it is necessary to strive to use a higher base of Ь b in the coded number system, since this reduces the number of cycles of operation of the device. However, the reduction in the number of cycles due to an increase in the base leads to a substantial increase in both the duration of the cycle itself and the volume of the equipment used. Even when using a binary-coded hexadecimal system, the calculation is 1t.e., when K 4 and N 2 1b), to implement each block of computing bit values of production, a constant memory with a capacity of 65536 8-bit binary words is required. And this does not allow to really ensure the high speed of operation of the blocks for calculating discharge product values even if the restrictions on the amount of equipment used in the device are removed. The implementation in the known device of blocks for calculating bit values of the product based on one-cycle combinational multipliers, for example, in the form of an iterative network, also does not ensure their high performance, since the time of formation of the result at their outputs is (2-Kl) f, where T is the signal delay on one cell of the network. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that in a multiplying device, containing a multiplicative register, AND blocks for calculating discharge values of the product (and the number of multiplicable bits, buffer registers of the first and second groups, the input of the first multiplier of each block for calculating discharge values of the product the output of the corresponding bit of the register of the multiplicand, the input of the second factor of each block for calculating the bit values of the product connected to the input of the device multiplier, the outputs of the values of the lower and higher times The rows of each block of calculation of the product's bit values are connected to the inputs of the corresponding buffer registers of the first and second groups, the output of the first buffer register of the second group is connected to the output of the device, the group of adders is entered, and the inputs of the -f -th group adder (.1 1,2, , .., and-l) are connected to the output of the i-th buffer register of the first and (-b buffer register of the second group), the inputs of the accumulator of the group are connected to the output of the I-th buffer register of the first group and the device correction input, the output of the sum and the transfer of each total The ora of the group is connected to the inputs of the first and second terms of the lower bit of the corresponding block for computing the bit values of the product.

. Pa figs. Figure 1 shows a block diagram of a device for multiplying numbers; in fig. 2 is one of the possible variants of joint implementation of the j-th block for computing the bit values of the product (, 2, ..., and the j-th group adder as an iterative network for the case of a binary-coded hexadecimal number system (, Y-4 and) 1 in Fig. 3 is a functional diagram of the cell used in the iterative network in Fig. 2.

The device contains (and-bit) register 1 multiplicand, and blocks 2 calculate the bit values of the product, in the buffer registers 3 of the first group, and buffer registers 4 of the second group, the group of And adders 5, the input b of the multiplier and the input 7 of the correction device , output 8 devices. The input of the first factor j-ro of the unit 2 for calculating the bit values of the product (Y 1, 2, ..., I) is connected to the output 9 of the j-th bit of register 1 multiplicand, the input of the second multiplier is to the input 6 of the multiplier of the device, the inputs of the first and the second component of the lower order - with the outputs of the sum and transfer of the j-th adder of the 5th group, the output of the 10th most significant bit is connected to the input of the j-th buffer register 3 of the first group and the output of the 11th lower order - with the input of the j-ro buffer register 4 second group. The inputs of the 1st soum of the 1st group 5 (, 2, ..., and -1) are connected to the outputs of the 1st buffer register 3 of the first group and (i + lj-ro buffer register 4 of the second group, inputs tf-ro adder 5 the groups are connected to the output of the -I-th buffer register 3 of the first group and the input 7 of the device correction, the output of the first buffer register 4 of the second group is connected to the output 8. The aggregate of the j-th block 2 for calculating the discharge values of the product of the j-th summer 5 and 3rd buffer registers 3 and 4 can be constructively executed in the form of a single module 12, implemented, for example, It is not difficult to include in this module, if deemed appropriate, the corresponding bit of register 1 of the multiplier as its third buffer register. This ensures a better one-way structure of the device.

In the device, the register 1 of the multiplicand and the buffer registers 3 and 4 can be built on push-pull synchronous D-triggers (the synchronization circuits are not shown in the drawing. It is assumed that all blocks 2 of calculating discharge product values and all adders 5 of the combinatorial type. In Fig. 2, as an example, the joint implementation of the j-th block 2 of calculating the binary values of the product and the j-th adder 5 as an iterative network for the case of a binary-coded six is shown. total number system, i.e. when

K 4 and. The iterative network contains twenty (in the general case

K + K) identical cells 13 and implements the functions of the j -th adder 5 and

0 of the jth block 2 for computing the bit values of the product (the lower row of the network of K cells 13 performs the function of adder 5, and the rest of the network of K cells 13 performs the function

5 of block 2 for computing bit values of product. It multiplies the binary-coded hexadecimal digit of the multiplicand X by the binary-coded hexadecimal digit.

multiplier Y y | at | y, (increasing indices with letter symbols in the direction of the higher bits) and adding to the younger binary-coded hexadecimal digit the result of the product of three binary coded hexadecimal digits U, M, and M. The digit of the multiplicand X arrives at

0 network input from the output of the 9th j register register of the multiplicand 1, the multiplier number. V - s, input 6 of the device, digits L and M - from the output of the j-ro buffer register 3 of the first group of the pseudo and number N - from the output of the (j + l) -ro buffer

5 registers 4 of the second group. At output 11 of the iterative network, the lower binary coded pole is formed, the result P is non-hexagonal, and the output 10 is the highest result p, in the form of two digits P and (figure P, the most significant bit of the result is formed in one-bit amounts, and - by bit transfers).

five

Each cell 13 of the network contains (FIG. 3) a one-bit binary adder 14, element I 15, and functions in accordance with the following logical expressions

0

Amount

Transferring T) (L © WE, where,

Transfers C from the outputs of the network cells 13 are transmitted from one of its rows to another and nowhere spread 5 along the row from right to left; therefore, My iterative network speed is determined by the value (K. + l), where T is the signal delay on one whose ke network. The considered variant of joint implementation of j.-ro block 2 for calculating the bit values of the product and the i-ro adder 5 is not the only one. So, for example, in order to increase speed, they can be implemented in the form of a tree in a certain way connected single-bit binary, adders (multi-layer Construction), or in some other known way. The common feature for all implementations is that the antiquities of the result of the output at output 10 are formed in the form of two digits (in a two-bit code). The multiplier operates as follows. In the initial state, the buffer registers 3 and 4 of all modules 12 are set to zero, register 1 of the multiplicator contains the unsigned and -unusable 2 -ich multiplicand code (n1 -bits binary multiplicand). Here it is assumed that the factors are binary-coded. Noah 2 is a numerical system, i.e. each bit of both a multiplier and a multiplier is a set of K binary numbers. In each of the first cycles of work. You are a device at its input 6 acting in parallel to the binary bits of the multitude, beginning with the lower order bits. At the same time, in the j-th block 2 of calculating the discharge values of the product, multiplication of the binary bits of the multiplicand arriving at its input of the first factor from the output of the 9 j -th 2-th bit of register 1 of the multiplicand, to the binary bits of the multiplier received at the input of the V.TOROG multiplier from the input 6 of the device, and adding to the younger binary bits the resulting 2-and -different product at its inputs of the first and second terms through;) -the adder of 5 K bins the bits of transmission {j + lj-ro of block 2, are formed data in the previous clock cycle in a single code and stored in the buffer register 4 (j + i) -ro module 12 and CI of the higher binary bits of the jth block 2, formed in the previous clock cycle in the two-wire code and stored in the buffer register 3 j-ro module 12. Thereafter, the low-order binary bits of the jth block 2 from its output 11 are formed in the single-digit code into the j-th buffer register 4, and the high-order bits of the output, represented in two-dy the code is from its output 10 to j. After the execution and the first cycles of operation of the device, zero input information is received at its input 6, and then additional steps are also taken during which the information stored in buffer registers 3 and 4 of all modules 12 is output from the device with the appropriate conversion. The output 2 of the AND-bit product of factors in the device is performed through its output 8 in the parallel-serial code {by K binary bits in each cycle). In the considered case, to the input 7 of the correction device in all its and additional clock cycles is supplied. To-bit binary code O ... OS. In those cases when it is necessary to obtain a rounded AND-bit product, it is necessary to submit / K-bit binary code .1 .... OOD to the input 7 of the correction in the first cycle of the device operation. This allows rounding of the work without additional time costs. Using the input device correction input 7 in a certain way, it is possible to simultaneously perform the operation of multiplying AND-bit numbers X and Y with summing to and most significant bits of the product of the i-bit term t, i.e. in one cycle of operation of the device, perform a complex operation O X + 2. For this it is necessary, during the cycles of operation of the device, starting from the second, to apply in each clock cycle to the input 7 the corrections of the device according to the U. binary bits of the term 2, beginning with its lower bits, and this addition of the term 2 can be either to rounded and older, or even to truncated and older ones. Multiplication and bit numbers in the proposed device {as in the well-known) can be performed in (and + 1) cycles, if, after the AND-th cycle, the contents of the buffer registers 3 and 4 of module 12 are submitted for final summation to the corresponding inputs of the high-speed three-input adder FIG. 1 such adder is not shown, but additional datapaths from the outputs of buffer registers 3 and 4 to the inputs of the adder are only marked with dashed lines. This may be particularly appropriate if, for example, the arithmetic logic unit of a computer contains a similar adder. Thus, the final product in the proposed device, as well as in the well-known; can

be formed for 2 nd or (and + 1) tak.tov. However, the duration of 1 block of one clock cycle in the proposed device is significantly reduced, because all blocks 2 of the calculation of the product digit values form at their output 10 the highest digit of the product bit in the form of two digits, i.e. in dvuhdnom code, and this eliminates the loss of time to bring in each step

ten

operation of the device dvuhridshlch icivi i in odnor l1i-.y. So, for example, in the implementation of blocks 2 in the pump; in the case of discharge values in the form of an iterative network, the duration of the pa6oTtJ cycle of the prototype device is approximately equal to (2-K-1) T, while in the proposed device it is (| + 1 / G, where TG is the delay of the Fia signal in a single network cell.

I

Vm.

N

Claims (1)

DEVICE FOR MULTIPLICATION, containing a register of multiplicable, AND blocks for calculating the digit values of the product (W is the number of bits of the multiplier), buffer registers of the first and second groups, and the input of the first factor of each block for calculating the bit values of the product is connected to the output of the corresponding bit of the register of the multiplier, the input of the second the factor of each unit for calculating the bit values of the product is connected to the input of the multiplier of the device, the outputs of the values of the least significant and highest bits of each unit for calculating the bit values values of the product are connected to the inputs of the corresponding buffer registers of the first and second groups, the output of the first buffer register of the second group is connected to the output of the device, characterized in that, in order to improve performance, the device additionally contains a group of adders, the inputs of the hth adder of the group (i = 1,2, ..., and-1) are connected to the outputs of the -i -th buffer register of the first group and the (ΐ + 1) -th buffer register of the second group, the yen inputs from the transfer wizard of each adder of the group are connected to the inputs of the first and ml of terms ml dshego vetstvuyushego discharge unit calculating values of row product. Of the i-th adder of the group with the output of the i-th buffer re-group and the input of the corructure, the outputs of the sum and FIG. 1 ns secondary