SU570047A1 - Device for reproducing of function - Google Patents

Description

one

The invention relates to computing and. can be used for direct and functional converters and specialized computing devices.

. An interpolator is known that interpolates a function with high order polynomials and contains an asynchronous type binary multiplication device, a binary counter, an adder, a fixed memory device (ROM), registers, an address device, an encoder, an output device, valve circuits, and a block. management 1. The disadvantages of this device are a large amount of hardware and low speed, since for each of the functions it is necessary to store a set of predetermined parameters in the ROM, using which the search function is calculated by executing many complex operations.

An electronic function generator with control is also known, using an interpolation method based on the coordinates of the points of inflection and containing a memory block, an interpolator, a comparator and a control block 2.

The disadvantages of this device are the complexity of the block; interpolations and low speed of operation, since the device first performs a sequential selection of inflection points and then performs the calculation using an interpolation formula containing complex operations (such as multiplication and division).

The closest in technical essence to the invention is a device for Reproducing functions, comprising a memory block, the input of which is connected by an output of a counter, the input of which is connected to the input of a device 3.

A disadvantage of this device is a large amount of equipment, since it contains four registers, a decoder and a memory unit with a capacity of Npop. and has a low speed, due to the many shipments between the registers, the decoder and the naMSjTH block.

The aim of the invention is to reduce the amount of equipment and increase the speed of the device.

This is achieved by introducing a trigger, two AND elements, an g OR element and an NOT element into the device, with the output of the memory block connected to the first input of the first element AND and the trigger input, the output of which is connected to the first input of the second element AND The jy cut is connected to the element NOT to the second input of the first. AND element and device input, outputs of the first and second AND elements are connected to the OR element inputs, the output of which is under- (keys to the device output.j5

The drawing is a diagram of the device. It contains a memory block 1, a counter 2,

trigger 3, elements AND 4. and 5, element NOT 6 element OR 7, input 8 and output 9 of the device.

The device works as follows. The y & 8 SHOCK 8 increments the argument, which is added to the contents of counter 2. In counter 2, the current value of the argument is generated, according to which the cell of memory 1 is selected. BIKE 1 memory contains one-bit cells; in which the function values are written. 3 "1 dChNE function increments for the corresponding value of the argument from the output of block 1 of the memory are fed to the trigger inputs 3 and the first entry of the first element AND 5. With the binary method of encoding the increments of the function and the argument, the output 9 is returned. the increments of the argument or the preceding value of the increments of the function with a clip-on sign for the negative increment of the argument and the increment of the FUNCTIONS is stored.40

For each value of the increment of argumentHlra, the current argument value is calculated at the counter 2, the function is incremented from the memory block, the value is stored in the O trigger, and the output of the forward function increment code 9 or the reverse code of the previous function increment is returned.

The device can be used in conjunction with the following analog-to-digital converters 1u1 and digital integrators and other devices in which the apryt HT is presented in increments.

The technical and economic effect of the invention H1 |} 1 (consists in the fact that the device has 55 5} N 11) is a smaller amount of equipment p9 sr (9neniyu with known devices

thus, in this device, the memory block contains N single-bit cells (,), with the value of N being selected from the following relationship:

U - 23ti (b + a} N,

where f is the maximum value of the derivative of the reproducible (function in a given range of variation of the argument a, and

 - given the accuracy of the playback function.

In known devices, the memory block contains N cells of Ogj N size, i.e. N fOfjNj, The considered device has V, N times less hardware costs than the known ones.

The speed of this device is determined by the sampling time of the function increment from the memory block and the flip-flop time of the trigger, which is significantly less than the execution time in known devices such operations as multiplication or division.

Claims (3)

1. US patent number 3678258, class. 235-15, 53, 1972. 2. US patent number 3813529, cl. 235-152, 1974. 3. A. L. Reichenberg and M. P. Fedorenko. Device for reproducing the sinus and cosine functions. Computer Engineering, Minsk, 1969, pp. 124-134.