SU894692A1 - Digital function generator - Google Patents

Description

(5) DIGITAL FUNCTION GENERATOR

I

The invention relates to automation and computing and can be used in specialized computing devices for reproducing functional dependencies with stringent storage space requirements.

A digital function generator is known that contains memory blocks, registers, switches, a shift block. A disadvantage of the known generator is a large amount of hardware.

Closest to the proposed is a digital function generator containing two registers, a decoder, two memory blocks, a multiplication unit, an adder, and two switches consisting of AND elements.

However, in a known generator, a piecewise linear function is interpolated digitally, interpolating the original function on a system of binary rational nodes,, 1, ... 2.

To do this, it is necessary to store 2N values of the function at the nodal points and 2 values of the derivative of the function at the same points. In total, this method requires 2 memory cells in two storage devices.

The purpose of the invention is to simplify the digital function generator.

The goal is achieved by the fact that the digital function generator, which contains the register of the most significant and the register of the least significant bits of the argument, the decoder, the memory block, the multiplier, the adder, the switch, the elements AND, the outputs of the register of the least significant bits of the argument are connected to the first group of inputs a multiplier whose outputs are connected to the first group of inputs of the adder, the outputs of the adder are outputs of a digital generator

20 functions, the outputs of the decoder are connected to the control, and the outputs of the memory unit to the information inputs of the switch, the outputs of which are connected 3. to the second group of inputs of the multiplication unit, contains a comparison circuit, a counter accumulating an adder, an element NOT and an additional AND element, and the outputs of the register of the higher bits of the argument are connected to the first group of inputs of the comparison circuit, and the outputs of the counter to the second group of inputs of the comparison circuit and the inputs of the decoder, the output of the comparison circuit through the element is NOT connected to the first inputs of the AND elements and the first input of the additional element AND, the second inputs of the elements AND are connected to the outputs of the switch, the outputs of the elements AND are connected to the input give the accumulating adder, the outputs of which are connected to the second group of inputs of the adder, the second input of the additional element AND is connected to the clock input of the digital function generator, and the output of the additional element I to the input of the counter. The drawing shows a digital generator @ p functions, functional diagram. The digital function generator contains a register of 1 high order and a register of 2 lower order arguments, a comparison circuit 3, a counter 4, a decoder 5, a memory block 6, a multiplication unit 7, accumulating adder 8, an adder 9 and 10, a switch consisting of elements AND 11, OR 12, element NOT 13 additional element AND 1A, clock input 15. The generator numerically calculates the value of the piecewise linear function y (x), which interpolates the function f (x) assigned to reproduction using a system of binary rational nodes j / 2 when, 1, ..., 2, when the value of the argument is fixed two registers so that the leading bits are arranged in the first register and the second mladshievo. The value of the generated piecewise-linear function with a fixed argument X is calculated according to the formula fCx V-iHCxj) vu) -fCV3bU-Xj), where f (x) is the value of the original function f (x) B is an unannual point Jl / 2. This value is calculated in the device as follows. (((x, - ,,) - Пх, (хо) (2 Accepting the notation (x -) - f (х-), we get (X) - & i 24x-X5) j; Xj Х5Х., hG Thus, at a fixed value of the arguments x on the device registers, the contents of the counter npo6eraet are values from O to J, i.e., the number of yMact approximations from first to current, and the values stored in memory block 6 are accumulated and then calculated The desired value of the approximating function y (x) is in accordance with 2. by one multiplication and one addition. Perform operation 2 (x-xj) for $ x. automatically by interpreting the code of the argument ejO; the ideal binary fraction in which the zap is fixed before the high bit. In the initial position, the value of f (xQ) is set on accumulator 8, the counter is set to O. In memory block 6, the values of the first differences d, j 0, 1,2, ... 1. The code of the argument value is reduced to registers 1 and 2. Since the contents of register 1 are not equal to the contents of counter 4, the output of the code comparison circuit 3 is O. Therefore, signal 1 from the output of the HE element is 13 opens the element AND N and the group of elements And 10. At the counter.: 4 through the element 14, clock pulses are received that fill the k counter. The contents of counter 4 are constantly decrypted by decoder 5 from memory 6 through a switch (elements 11 and OR 12) and a group of elements 10 and the values of the first differences arrive at the accumulating adder 8, where they are summed up in accordance with (1). On the J-OM cycle, the contents of counter C are equal to the contents of register 1 (the highest order of the argument). Signal 3 triggers at its output. Signal 1 appears. The counter is filled with clock pulses and AND 10 elements are closed. The last difference to the accumulating adder 8 is the difference. However, the second inputs of multiplication unit 7 from memory 6 receive the value the difference j, corresponding to the number of the approximation area set on the counter.

The variance is made according to 2) the least significant bits of the argument x and the difference: type j, and then in the adder 9 the required value of the approximating piecewise linear function y (x) is formed,

Thus, in the proposed device, in comparison with the known memory size, it is reduced by a factor of two.

Claims (2)

1. Authors certificate of the USSR W 711556, cl. G About F 1/02, 1977. 2. USSR author's certificate No. G About F 1/02, IS (prototype). n