SU437076A1 - Pulse frequency functional converter of two variables - Google Patents

Description

one

The invention relates to computational technology and it should be used as an independent functional unit, which provides pre-processing of information from frequency sensors when they are connected to a digital computer, as well as w / part of computing devices intended for direct processing of frequency-I1Mpulse signals.

An analog-to-digital device for reproducing functions of two variables is known, based on the Lagrange interpolation polynomial in a piecewise linear logical form, containing input converters, a storage unit, an interpolator, and an evaluation unit.

However, these devices are characterized by low accuracy of the implementation of the functional dependence (xiy), due to the faults of the analog-digital transformations, as well as the faults of the complex analog part of the converter-interpolator.

The purpose of the invention is psuvyschenie. functional transformation accuracy while maintaining the continuous nature of information processing. To accomplish this goal, a comparator, frequency dividers, a correction frequency shaping unit, a reversible counter, AND and OR circuits are entered into the device, the inputs of the comparator unit are connected to the second input of the device and the output of one of the frequency dividers, respectively; one of the outputs of the comparison unit, the other two outputs of the comparison unit are connected to the first inputs of the AND circuits, the second inputs of which through the correction frequency shaping unit are connected to the outputs of the interpolator, AIT1 from (OUTPUT which is connected to the inputs of the frequency dividers; the outputs of the AND circuits are connected to the first inputs of the OR circuits, the second inputs of which are connected respectively to the second input of the device and to the output of the second frequency divider, the outputs of the OR circuit are connected to the inputs of the reversible counter, the outputs are Which are connected to the inputs of the interpolator and the storage unit, the other inputs of which are connected to the outputs of the trigger states of the frequency-code converter, the frequency input connected to the interpolator, and the code outputs of the storage unit Connected to the corresponding inputs of the correction frequency shaping unit.

FIG. 1 shows a diagram of the proposed device; in fig. 2 - interpolator circuit.

Frequency-pulse functional converter (CHIFP) consists of interpolator 1, correction frequency shaping unit 2, storage unit 3, frequency-code 4 converter, comparison unit 5, AND 6 and OR 7 circuits, reversible counter 8, frequency dividers 9 and 10.

In the proposed device, the input F is connected to the input of the comparator unit 5, another input of the frequency divider 10 connected to the output, the installation input of which is connected to the output of the comparator unit 5, and the other two inputs are connected to the inputs of the AND 6 circuits. The second inputs of these circuits are connected to the output of the correction frequency shaping unit 2, and the outputs to the inputs of the corresponding circuits "OR 7. The second input of one of the circuits." OR 7 is connected to the input of the device, and the output is connected to the summing input of the reversing counter 8, the read input connected to the output another scheme "OR 7, the second input of which is connected to the output of frequency divider 9. The outputs of the reversible state of the counter 8 are connected to the inputs of the interpolator 1 and the storage unit 3, other inputs of the frequency-code converter connected to the output. 4, the frequency input (FX-Fxi) connected to one of the inputs of interpolator 1, and the input .- to the input FX of the device. The outputs of the storage unit 3 are connected to the corresponding inputs of interpolator 1, one of the outputs connected to the inputs of frequency dividers 9 and 10, and the other are connected to the inputs of the correction frequency shaping unit 2, the rest of the inputs connected to the code outputs of the storage unit 3.

Pulse frequency functional converter of two variables implements the dependence

N, (t) F, (i), F, (i) (1)

by reproducing the inverse function

(2)

in the feedback circuit of the frequency-pulse impulse balancing system, which forms the basis of the device circuit.

In order to increase the speed of the FPIC, a coarse channel is used, which periodically tests the resultant NZ code dynamically. The coarse channel (see Fig. 1) consists of the comparison circuit 5, the frequency shaping circuit of correction 2, the two circuits And 6, the frequency divider 10.

The principle of the coarse channel is based on comparing the input frequency frequency Gu (/) with the feedback frequency period Gos (due to inequality over time (r) -Hos (0, the correction + AN is generated.).

The scheme of the proposed device is as follows. The pulses of the input frequency FX are fed to the input of the frequency-code converter 4, where the code of the interval number is generated. From the frequency output of the frequency-code converter 4, the interpolator 1 is fed a difference signal FX-Fxi, which participates in the formation of the interpolating multiplier. In accordance with the codes of the converter 4 and the high-order bits of the reversible counter 8, the storage unit 3 connects the frequencies Fij, Fi + i, j to the interpolator tl input; Fij + i, / i + ij + i is the model of the ordinate of the function, in the interpolation nodes of the // - square of the definition domain partition. In addition, the forward and reverse codes of the low bits of the reversible counter S are supplied to the interpolator's input. Interpol torus, according to expressions for sequential linear Lagrange interpolation

/ + l - g

g - zi

(3)

+ UG

- g;

/ 4l

Where

 . U1 yijh U1 + 1 j

 4 I

Xs (1

X-xi

i l, 1 + 1 y. , x.- at 1 + 1.1 + 1

 - / - J

generates the frequency DFB, and it determines the value of the function f-1 inside the found square

5 partitions (ij).

The expressions g /, and g /, (3) are simulated by multiplying-dividing devices (MDU), implemented on the basis of the LTK trigger ring 11 scheme (see Fig. 2), at the outputs of which rectangular pulses are formed with filling coefficients

PX - FXI

and (4)

xi + l- xi

PKI + I - PXI

5 where F,., T

reference frequency.

The LTK 11 signals control the passage through the And 12, 13, 14, 15 impulses of the respective frequencies, Fi + i, 3, Pr, C +, i + l, j4-l

which is equivalent to multiplying the latter by

zaiolneniya coefficients (4).

The OR 16, 17 schemes summarize the pulse sequences, as a result of which at their outputs the average values of the frequencies are respectively

yy

FX-FXJ

p cX1 + 1 I g

1 1 - fi + i, j

Fxi

,

xi + l x

. G-, FX Fxi / g--.

Fj Fi,} + i

+ ./+i-Г -. (5) Fxi

F

Xi

The final expression for y (3) models 1c using binary multiplier circuits (DL) 18 and 19 and the “OR 20” scheme (see FIG. 2).

N ,,. j

, (6)

Pyj I N, j-, z,

where Nzi + i - N j corresponds to the lower unit of the code L / zj involved in determining the square of the partition of the domain of the definition of φ. From the output of the interpolator 1 - the frequency Foc, the frequency divider 9 and the “OR 7,.” Circuit go to the subtracting input of the reversible counter 8, the summing input of which

through another circuit “OR 7, the frequency pulses Fy are received. In the static mode, in the reversible mode of operation 8, a quantitative comparison of the pulses of the frequency Fy (t) and / oc is carried out (O and in case of their inequality (processing of the resultant code Nz (t) takes place, i.e. only the exact channel three) operates.

In the dynamic mode, i.e., when the error / gtspr-L greinal is exceeding the error of the coarse channel operation, the comparison unit 5 generates a hlLT signal allowing the passage through the appropriate And frequency circuit Fh from the correction frequency shaping unit 2, which is determined in such a way as to ensure the best convergence of the three minimum asparature costs. The formation of a per-period correction of the DLg occurs as long as the value of L gteor-L grenal “in becomes less than the error of the coarse channel. It is necessary to compare the synchronization of the PG periods (O and Gos (0 is achieved by initial setting of the frequency divider by 10 frequency pulses Fj (t)).

The static error of the considered converter has the following components: the discreteness error of the output code, the interpolation error, the error due to the code ripple. In turn, the fullness of interpolation is made up of a methodical, determined by the number of splitting wadrats, and instrumental, determined by the accuracy of a set of frequencies that simulate the ordinates of the function в at the interpolation nodes, and the accuracy of the operating units.

All components of the error can be reduced to the required value by a corresponding increase in the number of bits of the reversible counter, the volume of the storage unit and the corresponding choice of frequency ranges.

Previously it was assumed that the function одно is single-valued. If it is necessary to reproduce the ambiguous function φ-, the definition area (p (x, y) should be divided into sections, where φ is single-valued, and the converter circuit is supplemented with special blocks

determining these sections and the necessary switching at the inputs of the storage unit.

In the proposed device, non-uniform (ordered) splitting into intervals along the axis A is also possible; and 2. In this case, in a memory block, it is necessary to store and, according to the change of the arguments, to produce different values of the partition intervals.

Subject invention

A two-variable pulse frequency function converter containing an interpolator connected to a storage unit, a frequency-code converter connected to one of the device inputs, characterized in that, in order to increase

precision, a comparison block, a frequency divider, a correction frequency shaping unit, a reversible counter, AND and OR circuits are entered, the inputs of the comparison block are connected respectively to the second input of the device and the output of one of the frequency dividers, the setup input of which is connected to one of the the outputs of the comparison unit, the other two outputs of the comparison unit are connected to the first inputs of the circuits "And, the second inputs" that through the correction frequency generator are connected to the first outputs of the interpolator, one of the outputs of which is connected to the input ami frequency dividers; the outputs of the circuits "And connected to the first inputs of the circuits" OR, the second

the inputs of which are connected respectively to the second input of the device and to the output of the second frequency divider, the outputs of the OR circuit are connected to the inputs of the reversible counter, the outputs of the states of which are connected to the inputs of the interpolator and the storage unit, the other inputs of which are connected to the outputs of the trigger states of the converter -frequency code, frequency output connected to the interpolator, and code outputs of the storage unit are connected to the corresponding inputs of the correction frequency shaping unit.

Fig.2 4n, -N, j}