SU1171807A1 - Interpolating device - Google Patents

Abstract

The INTERPOLATION DEVICE contains the first and second counters, the first and second input registers, the memory block, the first buffer register and the control unit, the outputs of the first and second counters are connected to the address input of the memory unit, the control unit contains a group of elements AND, an address counter, trigger and an element, characterized in that, in order to increase speed, a second buffer register, two groups of modulo two modulators, three switches, a matrix multiplier and a result register, whose output is connected to device output and information inputs of the first and second buffer registers, the outputs of which are connected to the first information inputs of the first and second switches, respectively, the second information inputs of which are connected respectively to the input of the logical zero of the device and the outputs of modulators two of the first group, the output of the memory block is connected to the first information input of the third switch, the second information input of which is connected to the outputs of modulo-two adders of the second group, the outputs of the first o and the second input registers are connected to the third information inputs of the second and third switches, respectively, and the first inputs of the corresponding bits of modulo adders, respectively, of the first and second groups, the second inputs of modulo adders, two are connected to the input of the logical unit of the device and the fourth information input of the third switchboard, the information inputs of the first counter and the input register are connected to the input of the first argument of the device, the input of the second argument of which is connected to the information Ion inputs of the second counter and the input register, the outputs of the first and third switches are connected to the inputs of the coefficient of the first and second multipliers of the matrix multiplication body, the output of which is connected to the information input of the result register, moreover (a memory node and a pulse generator are entered into the control unit, the output of which is connected to the first input of the I element, the output of which is connected to the counting input of the address counter and the first inputs of the AND elements of the group, the second inputs of which are connected to the outputs according to The first bits of the memory node, the address input of which is connected to the output of the address counter, the installation input of the device in “About which is connected to the installation input of“ 1 trigger and the start input of the device; the readiness output of which is connected to the inverse trigger output, the direct output and the installation input in “About which are connected respectively to the second input of the AND element and the high-order output of the second group of outputs of the memory node, the outputs of the second group of the memory node are connected to control inputs first to third switches, the outputs from the first to tenth elements of the AND group are connected respectively to the summing input of the first counter, the synchronization input of the first counter, the synchronization input of the first input register, the input of the sum

Description

Mirovani - second counter, the subtraction input of the second counter, the synchronization input of the second counter, the synchronization input of the second input register, the synchronization input of the first buffer register, the synchronization input of the second buffer register and the synchronization input of the result register, the second inputs of modulators two from the second to the nth (n-times the order of the argument) of the first and second groups are connected to the outputs, respectively, from the first to the (n-1) -th same groups.

The invention is intended for use as a hardware extender in microprocessor systems and can be used in instrument engineering, control and information measuring systems.

The purpose of the invention is to increase speed.

FIG. 1 shows a diagram of the device; in fig. 2 is a control block diagram for the proposed device.

The device contains counters I and 2, input registers 3 and 4, memory block 5, groups of adders 6 and 7 modulo two, switches 8-10, buffer registers 11 and 12, matrix multiplier 13, result register 14 and control block 15. Counters 1 and 2 and registers 3 and 4 form blocks 16 and 17 of reception of argument codes. The control unit 15 comprises a pulse generator 18, an address of the memory node address 19, an address counter 20, a memory node 21, a trigger 22, a group of 23 elements AND, an element 24, an input "Start 25, outputs" Ready 26, "Control 27 and" Address 28.

The device works as follows.

When entering the g argument, blocks 16 and 17 of receiving the argument codes, arguments X and Y are divided into groups of higher bits Xc and Ye, which are entered into counters I and 2, respectively, and groups of lower order bits of arguments X and Y, which are mc into registers 3 and 4 respectively. The interpolation of variable functions is performed using the interpolation formula

Z f (x j + pb, Yi + k) (1-P) (1-q) fjj + p (1-q) (l-p) f4 + t + + Pqfmj-n,

where fij, i-i-ij,, fi-fijVi are the values of the functions corresponding to pairs of values of the nodal points of the arguments, x, viYj - i Yj + t. xirfYj i closest to (x j + ph),

(Yi + qk) h is a constant step of locating the nodal points along the X axis;

k is a constant step of locating the nodal points along the Y axis,

O p 1 is variable, determining the position of the argument X within the quantization step;

Q q 4.1 is variable, determining the position of the argument Y within the quantization step;

Xi - the nearest value of the nodal point along the X axis, less than the argument X;

y - the nearest value of the nodal point along the Y axis, less than the Y argument.

In the device for interpolation, Xj and Y / are the values of the higher bits of the arguments Xt and WD, entered into 5 counters 1 and 2, respectively. The codes read from these counters act as the address of memory block 5, the address word of which is formed by concatenating (combining) the values X | and Y, read from the counters. The p and q values represent the lower bits of the Um argument codes read from registers 3 and 4, respectively. The interpolation procedure for the values of functions of two variables is performed in the proposed device in 5 counts of 11 cycles. The computation process is controlled by control unit 15, one of the possible circuit implementations of which is shown in FIG. 2. The operation of the control unit starts at a signal from input 25 "Start. Upon completion of the calculation process, the control unit generates a signal at output 26 "Ready. Each control cycle of the device corresponds to one control word of the block. The output word is divided into the floor "Address and" Control 5 (outputs 28 and 27, respectively). The Address field determines which of the channels is included in the switches 8-10 when each of the calculation cycles is executed. The field Control for generating the write enable signals to the counters and registers 0 1,2,3, 4, 11, 12, and 14, and the signals defining the counting mode in counters 1 and 2. In each of the steps for calculating the functions of two variables, the following action

5 In the zero cycle, arguments X and Y are put into the argument receiving blocks. In this case, the higher bits of the XC and YC arguments are placed in counters 1 and 2, respectively, and the lower bits of the X and YK arguments are placed in registers 3 and 4, respectively . In the first cycle, the product is calculated (1-p) (1-q). Values 1-p and 1-q are formed by reading inversions p and q from registers 3 and 4 and adding one to lower-order bits of inversions using groups 6 and 7. Additional codes 1-p and 1-q generated in this way are fed through switches 9 and 10 to the inputs of the multipliers X and Y of the matrix multiplier 13, to the input of the summation To the matrix multiplier 13 in the first cycle-constant O through the switch 8. The result of the first cycle is entered from the register 14 of the result into the buffer register 12. In the second cycle the product ftj is formed (l-p) (1-q). The value of fj / npH is read from memory block 5, the address of which is the concatenation of X and Y /, and the product (1-p) (1-q) is read from register 12. The result of the calculation is entered from the register 14 of the result into the buffer register P. In the third cycle, the product p (1-q) is formed. In this case, from register 3, the direct value of the code p is read, and from register 4, the inversion of the code q, which goes to the adder 7. The values of p and 1-q are fed to the inputs of the factors X and Y of the matrix multiplier 13, which also as in the first and second clocks, the constant "O supplied by switch 8 is present. The result of the third cycle is entered from register 14 of the result into the buffer register 12. In the fourth cycle, the product p (1-q) f.jH is calculated. For this purpose, the contents of counter 1 are incremented by one, which ensures that the node 5 is addressable in block 5. The value of the node point of the function thus read is fed through the switch 9 to the input of the factor X of the matrix multiplier 13. To the input of the factor At the matrix multiplier 13 in this cycle, the value of the product is applied. p (1-q) from register 12, and to the summation input To matrix matrix multiplier 13 is the constant "O supplied through switch 8. The result of the calculation is entered from result register 14 to buffer register 12. Sum calculation (1 -p) (1-) fij + p {1-q) ft -ij For this purpose, the input to the summation of the matrix multiplier 13 is fed through switch 8 to the contents of register 11, in which the value (1-p) (1-q) fij is written , the input of the factor X of the matrix multiplier 13 is fed through the switch 9, the constant "1, and the input of the multiplier T of the matrix multiplier 13 is fed through switch 10, the contents of register 12, in which the value of p (1-q) fi4ii is written. The result obtained in the fifth cycle is entered from the result register 14 into the buffer register 11. In the sixth cycle, the product q (l – p) is calculated. To do this, from the register 3, the q code is read, and from the 4 register, the inversion of the p code, which is fed to the input of the matrix multiplier 13 through the adder 7 and the switch 10. The result of the operation from the result register 14 is entered into the buffer register 12. In the seventh cycle, producing q (lp) f5 / 44-For this purpose, the contents of counter 1 are decremented by one, and the contents of counter 2 are incremented by one, which ensures that the junction point fjj4.j is addressed in memory block 5. The value of the node point of the function thus read is fed through the switch 9 to the input of the multiplier X of the matrix multiplier 13. To the input of the matrix multiplier 13 in this step, the value q (l-p) is fed from the buffer register 12, and to the input of the summation To the matrix multiplier 13 - the constant "O supplied through the switch 8. The result obtained on the seventh clock cycle is entered from the register 14 of the result into the buffer register 11.

Claims (1)

DEVICE FOR INTERPOLATION, containing the first and second counters, the first and second input registers, a memory unit, the first buffer register and a control unit, the outputs of the first and second counters are connected to the address input of the memory unit, and the control unit contains a group of And elements, an address counter, a trigger and an And element, characterized in that, in order to improve performance, a second buffer register, two groups of adders modulo two, three switches, a matrix multiplier and a result register, the output of which is connected to the output, are introduced into it device house and information inputs of the first and second buffer registers, the outputs of which are connected to the first information inputs of the first and second switches, respectively, the second information inputs of which are connected respectively to the logical zero input of the device and the outputs of the adders modulo two of the first group, the output of the memory block is connected to the first the information input of the third switch, the second information input of which is connected to the outputs of the adders modulo two of the second group, the outputs of the first and second input registers are connected to the third information inputs of the second and third switches, respectively, and the first inputs of the corresponding bits of the adders modulo two, respectively, of the first and second groups, the second inputs of the adders modulo two are connected to the input of the logical unit of the device and the fourth information input of the third switch, information inputs the first counter and input register are connected to the input of the first argument of the device, the input of the second argument of which is connected to the information inputs of the counter and the input register, the outputs from the first to the third switches are connected to the inputs of the coefficients of the first and second factors of the matrix multiplier, the output of which is connected to the information input of the result register, and a memory node and a pulse generator are inserted into the control unit, the output of which is connected to the first input the And element, the output of which is connected to the counting input of the address counter and the first inputs of the And elements of the group, the second inputs of which are connected to the outputs of the corresponding bits of the first uppy memory unit outputs, the address input of which is connected to the output address counter set input "0" is connected to the setting input of "1" and the input start trigger device! the readiness output of which is connected to the inverse output of the trigger, the direct output and installation input of “0” which are connected respectively to the second input of the And element and the high-order output of the second group of outputs of the memory node, the outputs of the second group of the memory node are connected to the control inputs from the first to the third switches , outputs from the first to the tenth elements AND groups are connected respectively to the summation input of the first counter, the synchronization input of the first counter, the synchronization input of the first input register, the sum input SU „1171807 of the second counter, subtraction input of the second counter, second counter synchronization input, second input register synchronization input, first buffer register synchronization input, second buffer register synchronization input and result register synchronization input, the second adders modulo two from the second in the nth (n-th order of argument) first and second groups are connected to outputs from the first to (n-1) th of the same groups.