SU1215118A1 - Interpolation device - Google Patents

Abstract

The invention is intended to calculate function values in microprocessor systems and can be used in instrument engineering, control and information measuring systems. The aim of the invention is to reduce the memory size by using the nodal points of a function with an arbitrary position. Binding to a nodal point is accomplished by performing a one-bit address lookup procedure. The device contains a sequential address approximation register, an argument register, a memory block, a trigger, an intermediate value register, three switches and a multiplication unit. 1 il. i (lu s71

Description

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The invention relates to computing technology, is intended for use as a hardware extender in microprocessor systems and can be used in instrument engineering, control and information measuring systems.

The aim of the invention is to simplify the device by reducing the size of the memory block.

The drawing shows a block diagram of the proposed device.

The device contains trigger 1, memory block 2, sequential approximation block 3, argument register 4, intermediate result register 5, first, second and third switches 6, 7 and 8, respectively, block 9, calculating the function {).

The device works as follows.

The interpolation of the function (x) defined on the finite set of points X, X, Xs- .. Xj, ... X by two coordinates), F (), is performed in accordance with the expressions of the following form:

y (x) F, (X,) + F (XiVr,; And)

Xi6 X Ki, v, (2)

Where

(Xx.

(3)

The implementation of the interpolation expressions (1) - (3) is carried out in the device in two cycles. The control signals, generated by trigger 1 and block 3, determine the state of the gistros 4 and 5 and switches 6-8, depending on the operation cycle of the interpolation device.

In the first cycle, the number M of the nodal point of the interpolated function and the value P calculated in accordance with formula (3) are found. The first calculation cycle starts when the device arrives at the input C1 for interpolating the initial set signal. Trigger 1 is then set to one and the initial code for the bitwise search procedure is formed at the information output of block 3. Block 3 is implemented based on the K155IR17 information system. The initial value of the code will be 0111111111111111. Setting trigger I to one state ensures that the argument code X is received in register 4. Register synchronization

18 2

4 - dynamic, with a positive edge of the pulse at the trigger output A single signal at the control inputs of switches 6-8 causes the output C of these switches to come from input A. At the same time, the output of block 9 receives the output of register 4, in which the argument code X is written, the constant - 1 is presented to the input X of block 9, presented in the additional code, and the input-Y is the value of the node point Xj, calculated from the output of memory block 2 at the address generated at the information output of block 3. Procedure bitwise search value vodits in the device according to the method of the segment dividing in half, i.e., by Finding the root of the equation

X - Xj Oh,

(M

in which the variable is the value of X; read from memory block. The search procedure, the values are clocked by the C2 clock pulses, which are fed to the synchronization input of block 3. As a result of comparing the values of X and X; in the process of bitwise searching for a value, the sign bit of the output of block 9 is used. On receipt of each current sync pulse C2, in block 3, one bit of code D is calculated. In this connection, the duration of the first cycle of the interpolation procedure is equal to the number of bits in code 1), calculated from the information output of block 3, multiplied by the follow-up period C2. As block 9, it is convenient to use a matrix multiplier, since matrix multipliers have free entry of the term K.

The first interpolation cycle completes after obtaining the num- ber value. nodal point i at the information point of block 3. At the same time, a direct control signal appears at the control output of this block, zeroing the trigger 1, and inverting this signal, which records the f code from the output of block 9 to the register 5. As the control output when implementing an address calculating unit based on the K155IR17 IP uses the output immediately following the information output. In the process

Search this output is set to zero-value, which resets trigger 1.

In the second interpolation cycle, the actual calculation is performed using the interpolation formula (1). The control signal from trigger 1 transfers switches 6. -8 to the state where the code from input B arrives at output C. In this case, the interpolation coefficients F (X,) and P (L (/, counted from the first and second outputs of memory block 2 at address .1 calculated on the first interpolation cycle. Input B of block 9 receives code b from register 5. The calculation procedure is in accordance with formula (1) when the corresponding the arguments to the inputs of block 9 do not require any control signals. The second operation cycle of the device for interpolation at the output of block 9 forms the required value of the interpolated function.

Claims (1)

Invention Formula An interpolation device containing a sequential approximation block, an argument register and a memory block, the information inputs of the argument register are connected to the argument inputs of the device, the device start input is connected to the initial setup input of the sequential approximation block}, the information outputs of which are connected to the address inputs of the block memory, and the clock input is connected to the clock input of the device, characterized in that, in order to simplify the device by reducing the size of the memory block, it contains rigger, intermediate result register. three switches and a function calculation unit, the device start input is connected to the installation input of 1 trigger, the output of which is connected to the control inputs of the first, second and third switches and the synchronization input of the argument register, whose outputs are connected to the first group of information inputs of the first switch, output which is connected to the input of the XV-vK function calculation unit, the code of the result module of which is connected with the information input of the intermediate results register, and the device output, and the sign The output is connected to the information input of the sequential approximation unit, the output of the approximation sign of which is connected to the setup input of the trigger, and the inverse output of the approximation sign is connected to the C1 input of the intermediate results register, the first group of information inputs of the second switch is connected to the input group of the -1 code setting device, the output of the second switch is connected to the) input of the function calculation block  , the outputs of the first interpolation coefficient of the memory block are connected to the second group of information inputs of the first switch, the outputs of the second interpolation coefficient of the memory block are connected to the second group of information inputs of the second switch, the outputs of the nodal point code of the memory block are connected to the first group of information inputs of the third switch whose code is connected to the S input of the function calculation block x- +, the second group of information inputs of the third switch is connected to the outputs of the register span overall results. Editor A.Lezhnina Compiled by A. Chekanov Tehred S. Migunova Proofreader O. Lugov 908/57 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch of TP Patent, Uzhgorod, Proektna St., 4