SU1187176A1 - Device for impementing fast haar transform - Google Patents

Abstract

A DEVICE FOR IMPLEMENTING A FAST HAARA TRANSFORM containing a synchronizer, first and second delay elements connected in series, first, second and third blocks of shift registers, first and second subtractors, and the input of the first delay element is an information input of the device, characterized in that in order to simplify the device, it contains a clocked element. the delay ment, while the output of the first delay element is connected to the first inputs of the first and second adders-subtractors, the second inputs of which are connected to the output of the second delay element, the output of the sum of the second totalizer-subtractor is connected to the input of a clocked delay element, the output of which is connected to the third input of the first adder-subtractor, the output of the difference of which is connected to the information input of the first block of shift registro.v, information output of which is connected to the input of the first delay element, four The first input and the third input of the second adders, the outputs, respectively, of the sum of the first and the second difference of the adders-subtractors are connected to the information inputs of the corresponding second and third blocks from the shift registers, first, second, third, fifth, fifth, sixth and the seventh synchronizer outputs are connected respectively to the enable inputs of the operands of the first and second subtractors, 00 inputs of the receive information reception -4 of the second, first and third blocks ti shift register in and clock input OS I will give a clocked delay element and the first block of shift registers.

Description

The invention relates to computing and can be used in automation systems for processing and transmitting digital signals and images based on a fast conversion algorithm.

Haar (BPH), when the dimension of the input sample N K, where k and n are any positive integers.

The purpose of the invention is to simplify the device.

FIG. 1 shows a device diagram (N 3); in fig. 2 - time diagrams that show his work; in fig. 3 - computation graph.

The device diagram (FIG. 1) contains a synchronizer 1 clocked, delay elements 2 and 3, summators 4 and 5, clocked delay element 6, blocks 7–9 of shift registers. .

In the proposed example, the transformation consists of four stages, corresponding to performing the operations of multiplying by matrices R, Rg, R2, R. Moreover, at the first stage, the input vector f is multiplied by the matrix at the second — the product, noJiyiseHHoe at the first stage and representing co. the battle matrix F is multiplied by the matrix R, and so on.

The device is designed so that the final results of the conversion, rpyiniaf-iH obtained after each stage, are stored in blocks 7 and 9 until the complete conversion process is completed, and the intermediate components are placed in block 8, from where they are to the input of the device.

The device works as follows.

With each clock cycle, the discrete signals under study are successively fed to the input of delay element 2, which is also the device input. With the arrival of the second signal and the feed from the synchronizer 1 to the control input of the adder-subtractor 5 of the control signal, the inputs are switched, the difference between the first two components is calculated and its subsequent placement in block 7, with a preliminary feed of the signal from the synchronizer 1. With the arrival of the third signal switches

the inputs of the adder-subtractor 4, which calculates the sum of the first three components of the input signal, simultaneously switches the inputs of the adder-subtractor 5 which calculates the sum of the first two components. The result obtained in the code of the subtractor 4 is placed in block 8, and from the output of the subtractor 5 to the delay element 6. At the next cycle with the arrival of the fourth signal at the output of delay element 2, we will have a third signal shifted by one bit to the left, which corresponds to its multiplication by two. At the same time, from the output of the delay element 6 to the input of the adder-subtractor 4, the sum delayed by one clock (f + f2 switches the inputs of the adder-reader 4 and calculates the difference (fi + f2 fg 3, which is located in block 9 in the presence of synchronizer 1 of the control signal. With the arrival of the fifth signal, the inputs of the adder-subtractor 5 are switched, the difference is calculated (f.-fg then, if there is a control signal from the synchronizer 1, it is placed in block 7. Then the device works in a similar way until the last first, the 81st component of the input signal. Then the second stage of the conversion begins, realizing the multiplication F, -R-, and the intermediate conversion results are used as input signals, which were placed in block 8 in the first stage and represent the sum n three components of the original signal. According to the signal from synchronizer 1, these sums are successively fed into the device input with each beat. In both this and the subsequent third and fourth stages, the device operates in exactly the same way as in the first, while data at the third stage are stored in the unit 8, the sum of the original signal components ninth five which were calculated during the second stage, and the input data of n fourth step, - the sum of the original signal component 27 obtained in this third ne.

At the third stage, the multiplication of FyR is realized, and at the fourth, F .R-. After the fourth stage is completed, the final results of the transformation will be in blocks 7 and 9, except for the first coefficient, which is calculated at the end of the fourth stage and placed in block 8. The output of the coefficients in the sequence indicated by the transformation matrix F is provided by the arrangement of output buses of the shift register blocks in right order

1871764

In the time diagram, which explains the operation of the device (Fig. 2), TI denotes continuously generated input clock pulses, which follow with a frequency equal to the frequency of the input signals. TI 1, TI 2, ..., TI 7 enabling clock pulses produced on the output tires of synIQ 1 synchronizer 1 (Fig. 1 arrows a, b, ..., g). The presence of 1 in the line of the timing diagram means the presence of the corresponding enabling signal at a given time.

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Claims (1)

DEVICE FOR IMPLEMENTING A QUICK TRANSFORM OF HAAR, comprising a synchronizer, serially connected first and second delay elements, first, second and third 'blocks of shift registers, first and second adders-subtracters, the input of the first delay element being an information input of the device, characterized in that, in order to simplify the device, it contains a clocked electronic. a delay moment, while the output of the first delay element is connected to the first inputs of the first and second adders-subtracters, the second inputs of which are connected to the output of the second delay element, the sum output of the second adder-subtractor is connected to the input of the clock delay element, the output of which is connected to the third input of the first the adder-subtractor, the difference output of which is connected to the information input of the first block of shift registers, the information output of which is connected to the input of the first delay element, the fourth input to the first and third inputs of the second subtractor adders, the outputs, respectively, of the sum of the first and the difference of the second adder-subtracters are connected to the information inputs of the second and third blocks of the shift registers, the first, second, third, fourth, fifth, sixth and seventh outputs of the synchronizer are connected respectively to the resolution inputs receiving operands of the first and second adders-readers, inputs of permission to receive information of the second, first and third blocks of shift registers and clock tact inputs uemogo delay element and the first block of the shift registers. . SU., „1187176 Alustra 1187176