SU1619298A1 - Device for orthogonal walsh transform of digital signals over sliding interval - Google Patents

Abstract

The invention relates to computing and can be used for digital signal processing, even and odd sequences, in image processing systems, for digital filtering, data compression, spectral and correlation analysis, in communication systems, etc. The aim of the invention is to expand the scope by calculating the coefficients ordered by even and odd functions (for determining even EYH and odd sequences). The goal is achieved by the fact that the device contains registers 1 ... 1, adders-subtractors to, switches, register 4, reversing shift register 5, first 6 and second 7 switches. 3 il. 9

Description

Cfc

with

i

00

Fig.Z

The invention relates to automation and computing and can be used for digital signal processing, even and odd sequences, in image processing systems, for digital filtering, data compression, spectral and correlation analysis, in communication systems, etc.

The purpose of the invention is to expand the scope by calculating the transform coefficients ordered by even and odd functions (to determine even and odd sequences).

FIG. Figure 1 shows the fast Walt transform graph with even-odd ordering for N () 8 from the sequence Tx (1) tx (8) 1; in fig. 2 is a fast Walsh transform graph with an even-odd ordering on a skewer interval for N 4 from the sequences {x (1) -th x (4)}, {x (Hx (5) J, / x (3) fx ( 6) j; in Fig. 3 - a functional diagram of the device.

The device (fig.Z) contains a group of K registers, a group of K adders-subtractors, a group of K switches, register 4, reversing shift register 5 and switches 6 and 7, information input 8, outputs 9 and 10 of odd and odd function , counter 11 and a group of elements EXCLUSIVE OR

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The device works as follows.

The input sequence | x (1) f 4x (NH, representing the current values of the samples of the converted digital signal, with a frequency of backward pulses goes to the second input of the adder-subtractor 2 groups, which is triggered in each clock cycle, and to the information input of the register 1 groups where it is delayed by one clock cycle (the value of one signal sample is stored in the group register.) The output of switch 3 groups during each clock cycle is the sum and then the difference generated at the outputs of the totalizer-subtractor 24 groups, starting with the second t CTA (in the first cycle are generated and output sum and difference of the first two samples from the previous input sequence

1619298

Јx (0) -f-x (N-1) j). Register 1 (groups and

switch 3

tovam

ten

15

20

25

thirty

40

45

50

55

The f groups are controlled by the signal 1V) (from the first such input device input a.

Data from the output of the switch 3, the groups go to the second input of the adder

2, -1

subtractor 2n group and on information

the first input of the group 1 register, which is controlled by the clock signal 2 from the first clock input of the first group with a frequency of 2fTiB) ("In the register" group, data is delayed by four clock cycles. During each clock cycle of the register 1 group in odd clocks at the output of the switch Rear Group which is controlled by the signal 3 s of the first clock input of the second group, the output from the results: the sum, then the difference, and in even-numbered intervals the difference, then the sum generated at the outputs of the totalizer-subtractor 2 groups;

x (j) + x (j + 4), x (j) -x (j + 4), j 1,3,5, ...

x (j) x (j + 4), x (j) + x (j + 4)

L 2,4,6, ...

starting from the fifth clock cycle. During the first four clock cycles, the sum and difference results, the difference and the sum of two pairs of samples, consisting of the first, are generated and output; four samples from the previous input sequence.

Data from the output of the (1-1) th (, K-2) 35 switch of the b group is fed to the second input of the adder-subtractor 2 {group and to the information input of the register 1g group with a clock frequency of 2 fr. & X. X, in register 1 group, which is controlled by a clock signal from the (1-1) th clock input of the first group, the data is delayed by 4 clock cycles. The output of the switch group 3g, controlled by the signal from the (1-1) clock input of the second group, the results for each clock cycle of the register I g of the group in odd cycles are the results: sum, then the difference, and in even cycles the difference then the sum formed in accordance with the conversion graph (Fig.2) at the outputs of the adder-subtractor 2 groups:

x (j) + x (), x (j) -x (j + 4 (), j 1,3,5, ...

x (j) -x (j + 4H), x (j) + x (), j 2,4,6, ...

switch 3

tovam

five

0

five

0

0

five

0

f groups are controlled by a 1-tv signal) (from the first clock input of devices a.

Data from the output of the switch 3, the group is fed to the second input of the adder2, -1,

subtractor 2n group and the information input of register 1 group, which is controlled by a clock signal 2 from the first clock input of the first group, with a frequency of 2fTiB) ("In register" group "data is delayed by four clock cycles. During each clock cycle of register 1 group in odd clocks to the output of the switch Rear of the group, which is controlled by the signal 3 from the first clock input of the second group, the results are displayed: sum, then the difference, and in even cycles - the difference, then the sum generated at the outputs of the subtractor 2 of the group;

x (j) + x (j + 4), x (j) -x (j + 4), j 1,3,5, ...

x (j) x (j + 4), x (j) + x (j + 4)

L 2,4,6, ...

starting from the fifth clock cycle. During the first four clock cycles, the sum and difference results, the difference and the sum of two pairs of samples, consisting of the first, are generated and output; four samples from the previous input sequence.

The data from the output of the (1-1) th (, K-2) 5 switch b group is fed to the second input of the adder-subtractor 2 {group and to the information input of the register 1g group with a clock frequency of 2 fr. &Amp; x, in register 1 group, which is controlled by a clock signal from the (1-1) th clock input of the first group, the data is delayed by 4 clock cycles. The output of the switch 3g of the group controlled by the signal from (1-1) is the clock input of the second group, during each clock cycle of the register I g of the group in odd clock cycles, the results are summed, then the difference, and in even clock cycles the difference then the sum formed in accordance with the conversion graph (Fig. 2) at the outputs of the adder-subtractor 2 groups:

x (j) + x (), x (j) -x (j + 4 (), j 1,3,5, ...

x (j) -x (j + 4H), x (j) + x (), j 2,4,6, ...

516

starting with 4J + 1-ro tact. During the first 4J (ticks, the sum and difference, difference and sum 2, sample pairs consisting of the first 2J samples from the previous input sequence are formed and output to the switch 3g output.

From the output of the (k-1) -ro switch of the group, data is fed to the second input of the adder-subtractor of the 2nd group and to the information input of the register 1 ,,

(/

groups with a clock frequency of 2 f f.gx where they are delayed by 4 clock cycles. During each clock cycle of register 1 (the group controlled by the signal 7 from the second clock input of the device, the odd numbers through the switch 3 groups into the register 4 are entered into the sums, which are the coefficients xc, (j) conversion with odd numbers, the emphasis derived from even Walsh functions of the first sequence Gx (1) (N) |, and through switch 6 to the reverse shift register 5, differences are written, which are xs (j) transform coefficients with odd numbers in reverse order , emphasis these odd functions, formed at the outputs of the totalizer-subtractor of the 2Y group:

x ° (j) x (j) + x (j + 4KI), xS (j + N / 2) x (j) -x (j + 4M), j 1,3,5, ... N / 2- one

V

starting with the 4 + 1 bar. In the even clock cycles in register 4, the differences are written, which are the xj (j) conversion coefficients with even numbers, ordered by the even Walsh functions, and the reversing shift register 5 is added to the x (j) conversion coefficients even numbers in the reverse order of their following, which are ordered by odd functions and formed at the outputs of the totalizer-reader 2 and groups:

x, (j) x (j) -x (i + 4),

x (j + N / 2) x (j) + x (), j 2,4,6, .. ,, N / 2

Starting from the 4th cycle. During the first 4 clock cycles, the transform coefficients for

$ 9298

even functions, and one of the Communicator 6 - coefficients are odd-numbered functions from the previous input sequence 1: and.

Thus, the current values of the N / 2 coefficient, ordered by even functions, are formed at the output of the switch 3 to the group by arrival

10 N-ro sampling; and the input signal, a, and recorded in register 4. The remaining N / 2 coefficients, ordered by non-i-net functions, are formed at the switch output o and recorded in pe ™

15 verssional register 5 SDPGT, On the arrival of the next N + 1 -.- o gtccount of the input signal, we simultaneously read the conversion factors for the even functions from the register

20 4 and converting in reverse order from the reversing shift register 5 and the coefficient l to the conversion by odd functions that are output to the output of the switch 7 with a clock frequency

25 2 to f TiBX. At the same time, the shift to register 4 and reversing shift register 5 is new: the current values of the coefficients are one-time and from the backing sequence x (2) -rx (N + l) f h, etc.

The shift register of the reverse shift register 5 and the switch / is carried out by signal 6 from the third clock input of the device.

35

Claims (1)

Invention Formula A device for orthogonal transformation of digital signals over 40 Walshs on a sliding interval containing a group of K (2 is the pre-designation dimension) of registers, a group of K adders-subtractors, a group of K switches, and the output of the k-th (k 1, K) group register connected to the first / input of the k-ro group subtractor, the output of the sum AND THE DIFFERENCES OF WHICH IS CONNECTED - Respectively to the first and second informational inputs of the k-ro switchboard group, the output of the pth switch (p1, K-1) of the switchboard group is connected to the information input of the (k + 1) -ro register of the group and the second input (K + O of the sum of the group’s 5 subtractor, and the second the input of the first totalizer-subtraction of the group is connected to the information input of the first register of the group and is an information input of the interface, characterized in that, in order to expand the scope of application by calculating coefficients ordered by even and odd functions, a register, first and second switches and a reverse shift register, the information input of which is connected to the output of the first switch, are entered, the first and second informational inputs of which are connected to the outputs of the sum and difference of the K-th group adder-subtractor, the output of the K-th group switch, respectively 15 connected to the information input of the register, the output of which is the output of the coefficient of even function of the device, the output of the coefficient of odd FUNCTION WHICH IS OUTPUT the second switch, the first and second 2o informational inputs of which are connected respectively to the direct and common ") X &) § HU n WITH I § “With S " - addition of FIG. I. 0 five about The output outputs of the reverse shift register, the clock input of the first group register is connected to the control input of the first group switch and is the first clock input of the device, the second clock input of which is the interconnected clock inputs of the K-th group register, register and reverse shift register the control inputs of the K-th group switch and the first switch, the shift control input of the reverse shift register is connected to the control input of the second switch and is the third clock input The devices, the t-th (, K-2) clock inputs of the first and second groups are respectively the clock input of the (t + 1) -th group register and the control input of the (t + 1) -th group switch.  getitian FIG. 2